Datasheet

A1
A1
E0
T
E1
T
E2
Microprocessor
E3
T
DDR2
Controller
T
AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 6-31. CLK and ADDR_CTRL Routing Specification
(1)
No Parameter Min Typ Max Unit Notes
1 Center to center DQS-DQSN spacing 2w
2 CK differential pair Skew Length Mismatch
(2)
25 Mils See Note
(1)
3 CLKB to CLKC Skew Length Mismatch 25 Mils
4 Center to center CLK to other DDR2 trace spacing 4w See Note
(3)
5 CK/ADDR_CTRL nominal trace length CACLM-50 CACLM CACLM+50 Mils See Note
(4)
6 ADDR_CTRL to CLK Skew Length Mismatch 100 Mils
7 ADDR_CTRL to ADDR_CTRL Skew Length Mismatch 100 Mils
8 Center to center ADDR_CTRL to other DDR2 trace 4w See Note
(3)
spacing
9 Center to center ADDR_CTRL to other ADDR_CTRL 3w See Note
(3)
trace spacing
10 ADDR_CTRL A to B, ADDR_CTRL A to C, Skew Length 100 Mils See Note
(1)
Mismatch
11 ADDR_CTRL B to C Skew Length Mismatch 100 Mils
(1) Series terminator, if used, should be located closest to AM3517/05.
(2) Differential impedance should be 100-ohms.
(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(4) CACLM is the longest Manhattan distance of the CLK and ADDR_CTRL net classes.
Figure 6-29 shows the topology and routing for the DQS and Dx net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
Figure 6-29. DQS and Dx Routing and Topology
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 147
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