Datasheet

Microprocessor
DDR2
vo DDR2 on One Chip Select
sdrc_cs0
CS#
CS#
ODT
ODT
sdrc_odt
DDR2
AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 6-33. SDRC_STRBENx Routing Specification
(1)(2)
No. Parameter Min Typ Max Unit Notes
1 SDRC_STRBEN0 Length F CKB0B1 See Note
(3)
SDRC_STRBEN1 Length F CKB0B2 See Note
(4)
3 Center to center SDRC_STRBENx to any other trace spacing 4w
4 DQS/Dx nominal trace length DQLM-50 DQLM DQLM+50 Mils
5 SDRC_STRBENx Skew 100 Mils See Note
(5)
(1) STRBENx termination resistors should be placed close to AM3517/05 STRBENx signal (not close to STRBEN_DLYx signal).
(2) Ensure signal velocities across different layers are taken into account when calculating STRBENx length. For example, if DQS0 and
DSQ1 are 1inch each, and DQS0 is on a layer that is 10% faster, use 1.1inch as the length for DQS0.
(3) CKB0B1 is the sum of the length of the CLK (the portion that goes to the memory associated with DQS0 and DQS1) plus the average
length of the DQS0 and DQS1 differential pairs.
(4) CKB0B2 is the sum of the length of the CLK (the portion that goes to the memory associated with DQS2 and DQS3) plus the average
length of the DQS2 and DQS3 differential pairs.
(5) Skew from CKB0B1 or CKB0B2.
6.4.2.2.12 On Die Termination (ODT)
ODT should only be used with 1 chip select as shown in Figure 6-31. If using sdrc_cs0 and sdrc_cs1,
sdrc_odt should not be used. ODT signals should be tied off at the memory.
Figure 6-31. ODT Connection Using One Chip select (sdrc_cs0)
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 149
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