Datasheet

VDIN_D[xx]
VDIN_HD
(Falling Edge)
VDIN_HD
(Rising Edge)
VF19
VF20
VF18
SPRS550-003
VDIN_CLK
(Falling Edge)
VF12,
VF13, VF14
VDIN_CLK
(Rising Edge)
VDIN_HD,
VDIN_VD,
VDIN_FIELD
VF15, VF16,
VF17
VF12, VF13, VF14
VF15, VF16,
VF17
SPRS550-002
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Figure 6-33. VPFE Output Timings
Figure 6-34. VPFE Input Timings With VDIN0_HD as Pixel Clock
6.5.2 Display Subsystem (DSS)
The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or
internal (SRAM) memory on an LCD panel or a TV set. The DSS integrates a display controller. It can be
used in two configurations:
• LCD display support in:
– Bypass mode (RFBI module bypassed)
– RFBI mode (through RFBI module)
• TV display support (not discussed in this document because of its analog IO signals)
The two display supports can be active at the same time.
6.5.2.1 LCD Display Support in Bypass Mode
Two types of LCD panel are supported:
• Thin film transistor (TFT) or active matrix technology
• Supertwisted nematic (STN) or passive matrix technology
Both configurations are discussed in the following paragraphs.
152 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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