Datasheet

dss_pclk
dss_vsync
dss_hsync
dss_acbias
dss_data[23:0]
DL4
DL5
DL3
DL0
DL2
DL1
030-061
AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
6.5.2.1.1 LCD Display in TFT Mode
Table 6-36 assumes testing over the recommended operating conditions (see Figure 6-35).
Table 6-36. LCD Display Interface Switching Characteristics in TFT Mode
(1)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
DL0 t
d(PCLKA-HSYNCT)
Delay time, dss_pclk active edge to dss_hsync transition -4.215 4.215 ns
DL1 t
d(PCLKA-VSYNCT)
Delay time, dss_pclk active edge to dss_vsync transition -4.215 4.215 ns
DL2 t
d(PCLKA-ACBIASA)
Delay time, dss_pclk active edge to dss_acbias active level -4.215 4.215 ns
DL3 t
d(PCLKA-DATAV)
Delay time, dss_pclk active edge to dss_data bus valid -4.215 4.215 ns
DL4 t
c(PCLK)
Cycle time
(2)
, dss_pclk 13.468 ns
DL5 t
w(PCLK)
Pulse duration, dss_pclk low or high 6.06 7.46 ns
c
load
Load capacitance 25 pF
(1) The capacitive load is equivalent to 25 pF.
(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the
DISPC_DIVISOR register.
Figure 6-35. LCD Display in TFT Mode(1) (2) (3) (4)
(1) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
(2) The pixel clock frequency is programmable.
(3) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.
(4) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 153
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