Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 6-55. McBSP2 Timing Requirements - Falling Edge and Transmit Mode (continued)
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSXV) mcbsp2_fsx Slave
valid after
Full Cycle 1.0 1.0 ns
mcbsp2_clkx
Slave
active edge
Table 6-56. McBSP2 Switching Characteristics - Falling Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp2_clkx active 0.2 14.8 0.2 14.8 ns
FSXV) edge to mcbsp2_fsx valid
B8 td(CLKXAE- Delay time, Master 0.6 14.8 0.6 14.8 ns
DXV) mcbsp2_clkx
Slave 0.6 14.8 0.6 14.8 ns
active edge to
mcbsp2_dx
valid
6.6.1.1.3 McBSP3
6.6.1.1.3.1 McBSP3 Multiplexed on McBSP3 Pins
The following tables show the timing conditions and switching characteristics for McBSP3 multiplexed on
McBSP3 pins.
Note: All timings apply only to Set #1- multiplexing on mcbsp3 pins.
Table 6-57. McBSP3 (Set #1) Timing Requirements - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 7.5 7.5 ns
CLKXAE) mcbsp3_dr Master
valid before
Half Cycle 7.7 7.7 ns
mcbsp3_clkx
Slave
active edge
Full Cycle 5.6 5.6 ns
Master
Full Cycle 5.8 5.8 ns
Slave
B4 th(CLKXAE- Hold time, Half Cycle 8.3 8.3 ns
DRV) mcbsp3_dr Master
valid after
Half Cycle 7.7 7.7 ns
mcbsp3_clkx
Slave
active edge
Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp3_fsx Slave
valid before
Full Cycle 5.8 5.8 ns
mcbsp3_clkx
Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSV) mcbsp3_fsx Slave
valid after
Full Cycle 1.0 1.0 ns
mcbsp3_clkx
Slave
active edge
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 161
Submit Documentation Feedback
Product Folder Links: AM3517 AM3505