Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-58. McBSP3 (Set #1) Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp3_clkx active 0.2 22.2 0.2 22.2 ns
FSXV) edge to mcbsp3_fsx valid
Table 6-59. McBSP3 (Set #1) Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp3_fsx Slave
valid before
Full Cycle 5.8 5.8 ns
mcbsp3_clkx
Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSXV) mcbsp3_fsx Slave
valid after
Full Cycle 1 1 ns
mcbsp3_clkx
Slave
active edge
Table 6-60. McBSP3 (Set #1) Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, mcbsp3_clkx active 0.2 22.2 0.2 22.2 ns
FSXV) edge to mcbsp3_fsx valid
B8 td(CLKXAE- Delay time, Master 0.6 22.2 0.6 22.2 ns
DXV) mcbsp3_clkx
Slave 0.6 22.2 0.6 22.2 ns
active edge to
mcbsp3_dx
valid
Table 6-61. McBSP3 (Set #1) Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
tsu(DRV- Setup time, Half Cycle 7.5 7.5 ns
CLKXAE) mcbsp3_dr Master
valid before
Half Cycle 7.7 7.7 ns
mcbsp3_clkx
Slave
active edge
Full Cycle 5.6 5.6 ns
Master
Full Cycle 5.8 5.8 ns
Slave
th(CLKXAE- Hold time, Half Cycle 8.3 8.3 ns
DRV) mcbsp3_dr Master
valid after
Half Cycle 7.7 7.7 ns
mcbsp3_clkx
Slave
active edge
Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FXSV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp3_fsx Slave
valid before
Full Cycle 5.8 5.8 ns
mcbsp3_clkx
Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
FSXV) mcbsp3_fsx Slave
valid after
Full Cycle 1.0 1.0 ns
mcbsp3_clkx
Slave
active edge
162 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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