Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-73. McBSP4 Timing Requirements - Rising Edge and Receive Mode (continued)
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
B3 tsu(DRV- Setup time, Half Cycle 7.5 7.5 ns
CLKXAE) mcbsp4_dr Master
valid before
Half Cycle 7.7 7.7 ns
mcbsp4_clkx
Slave
active edge
Full Cycle 3.2 3.2 ns
Master
Full Cycle 4.2 4.2 ns
Slave
B4 th(CLKXAE- Hold time, Half Cycle 7.7 7.7 ns
DRV) mcbsp4_dr Master
valid after
Half Cycle 5.2 5.2 ns
mcbsp4_clkx
Slave
active edge
Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp4_fsx Slave
valid before
Full Cycle 4.2 4.2 ns
mcbsp4_clkx
Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 5.2 5.2 ns
FSV) mcbsp4_fsx Slave
valid after
Full Cycle 1.0 1.0 ns
mcbsp4_clkx
Slave
active edge
Table 6-74. McBSP4 Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 16.6 0.2 16.6 ns
FSXV) mcbsp4_clkx
active edge to
mcbsp4_fsx
valid
Table 6-75. McBSP4 Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B5 tsu(FSXV- Setup time, Half Cycle 7.7 7.7 ns
CLKXAE) mcbsp4_fsx Slave
valid before
Full Cycle 3.7 3.7 ns
mcbsp4_clkx
Slave
active edge
B6 th(CLKXAE- Hold time, Half Cycle 1.0 1.0 ns
FSXV) mcbsp4_fsx Slave
valid after
Full Cycle 1.0 1.0 ns
mcbsp4_clkx
Slave
active edge
Table 6-76. McBSP4 Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT
MIN MAX MIN MAX
B2 td(CLKXAE- Delay time, 0.2 16.6 0.2 16.6 ns
FSXV) mcbsp4_clkx
active edge to
mcbsp4_fsx
valid
166 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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