Datasheet

hsusbx_clk
hsusbx_stp
hsusbx_dir_&_nxt
hsusbx_data[7:0]
Data_OUT Data_IN
HSU1
HSU0
HSU1
HSU4
HSU2 HSU2 HSU6
HSU3
HSU5
030-087
AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 6-108. High-Speed USB Timing Requirements 12-bit Master Mode
(1)
(continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
t
h(CLKH-NXT/IV)
Hold time, hsusbx_nxt valid after hsusbx_clk rising edge 0.2 ns
HSU5 t
s(DATAV-CLKH)
Setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge 7.5 ns
HSU6 t
h(CLKH-DATIV)
Hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge 0.2 ns
Table 6-109. High-Speed USB Switching Characteristics 12-bit Master Mode
(1)
N O. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
HSU0 f
p(CLK)
hsusbx_clk clock frequency 60 MHz
t
j(CLK)
Jitter standard deviation
(2)
, hsusbx_clk 200 ps
HSU1 t
d(CLKH-STPV)
Delay time, hsusbx_clk high to output hsusbx_stp valid 13 ns
t
d(CLKH-STPIV)
Delay time, hsusbx_clk high to output hsusbx_stp invalid 2 ns
HSU2 t
d(CLKH-DV)
Delay time, hsusbx_clk high to output hsusbx_data[0:7] valid 13 ns
t
d(CLKH-DIV)
Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid 2 ns
t
R(do)
Rise time, output signals 2 ns
t
F(do)
Fall time, output signals 2 ns
(1) In hsusbx, x is equal to 1 or 2.
(2) The jitter probability density can be approximated by a Gaussian function.
In hsusbx, x is equal to 1 or 2.
Figure 6-50. High-Speed USB 12-bit Master Mode
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 183
Submit Documentation Feedback
Product Folder Links: AM3517 AM3505