Datasheet

1-WIRE
tRSTH
tPDLtPDHtRTSL
030-099
HDQ
Break
0_(LSB )
1 6 7_(MSB)
tRSPS
0_(LSB )
1
6
Command _byte_written Data_byte_received
030-098
HDQ
tDW1
tDW0
tCYCD
030-097
HDQ
tHW1
tHW0
tCYCH
030-096
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Figure 6-58. HDQ Read Bit Timing (Data)
Figure 6-59. HDQ Write Bit Timing (Command/Address or Data)
Figure 6-60. HDQ Communication Timing
6.6.10.2 1-Wire Protocol
Table 6-124 and Table 6-125 assume testing over the recommended operating conditions (see Figure 6-
61 through Figure 6-63).
Table 6-124. 1-Wire Timing Requirements
PARAMETER DESCRIPTION MIN MAX UNIT
t
PDH
Presence pulse delay high 68 s
t
PDL
Presence pulse delay low 68 t
PDH
t
RDV
+ t
REL
Read bit-zero time 102
Table 6-125. 1-Wire Switching Characteristics
PARAMETER DESCRIPTION MIN TYP MAX UNIT
t
RSTL
Reset time low 484 s
t
RSTH
Reset time high 484
t
SLOT
Write bit cycle time 102
t
LOW1
Write bit-one time 1.3
t
LOW0
Write bit-zero time 101
t
REC
Recovery time 134
t
LOWR
Read bit strobe time 13
Figure 6-61. 1-Wire Break (Reset) Timing
192 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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