Datasheet

i2cX_sda
i2cX_scl
STOPSTART REPEAT
I1 I2 I3 I4I6I5 I7
030-094
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
6.6.11.2 I
2
C High-Speed Mode
Table 6-127. I
2
C High-Speed Mode Timings
(1) (2)
1.8V, 3.3V
NO. PARAMETER UNIT
MIN MAX
f
SCL
Clock frequency, i2cX_scl 3.4 MHz
I1 t
w(SCLH)
Pulse duration, i2cX_scl high 60
(3)
s
I2 t
w(SCLL)
Pulse duration, i2cX_scl low 160
(3)
s
I3 t
su(SDAV-SCLH)
Setup time, i2cX_sda valid before i2cX_scl active level 10 ns
I4 t
h(SCLHSDAV)
Hold time, i2cX_sda valid after i2cX_scl active level 70 s
I5 t
su(SDAL-SCLH)
Setup time, i2cX_scl high after i2cX_sda low 160 s
(for a START
(4)
condition or a repeated START
condition)
I6 t
h(SCLHSDAH)
Hold time, i2cX_sda low level after i2cX_scl high level 160 s
(STOP condition)
I7 t
h(SCLHRSTART)
Hold time, i2cX_sda low level after i2cX_scl high level 160 ns
(for a repeated START condition)
t
R(SCL)
Rise time, i2cX_scl 10 40 ns
t
R(SCL)
Rise time, i2cX_scl after a repeated START condition 10 80 ns
and after a bit acknowledge
t
F(SCL)
Fall time, i2cX_scl 10 40 ns
t
R(SDA)
Rise time, i2cX_sda 10 80 ns
t
F(SDA)
Fall time, i2cX_sda 10 80 ns
(1) In i2cX, X is equal to 1, 2, or 3.
(2) The device provides (via the I
2
C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to
bridge the undefined region of the falling edge of i2cx_scl.
(3) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. t
w(SCLL)
> 2 t
w(SCLH)
.
(4) After this time, the first clock is generated.
Figure 6-65. I
2
C High-Speed Mode(1) (2) (3)
(1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. t
w(SCLL)
> 2 x t
w(SCLH)
.
(2) In i2cX, X is equal to 1, 2, or 3.
(3) After this time, the first clock is generated.
Table 6-128. Correspondence Standard vs. TI Timing References
AM3517/05 STANDARD-I
2
C
S/F Mode HS Mode
f
SCL
F
SCL
F
SCLH
I1 t
w(SCLH)
T
HIGH
T
HIGH
I2 t
w(SCLL)
T
LOW
T
LOW
I3 t
su(SDAV-SCLH)
T
SU;DAT
T
SU;DAT
I4 t
h(SCLH-SDAV)
T
SU;DAT
T
SU;DAT
I5 t
su(SDAL-SCLH)
T
SU;STA
T
SU;STA
I6 t
h(SCLH-SDAH)
T
HD;STA
T
HD;STA
I7 t
h(SCLH-RSTART)
T
SU;STO
T
SU;STO
I8 t
w(SDAH)
T
BUF
196 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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