Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-140. MMC/SD/SDIO Timing Requirements Standard MMC Mode and MMC Identification
Mode
(1)(2)(3)
NO. PARAMETER 1.8 V 3.3V UNIT
MIN MAX MIN MAX
Standard MMC Mode and MMC Identification Mode
MMC/SD/SDIO Interface 1
MMC3 t
su(CMDV-CLKIH)
Setup time, mmc1_cmd valid before 2.13 2.41 ns
mmc1_clk rising clock edge
MMC4 t
h(CLKIH-CMDIV)
Hold time, mmc1_cmd valid after mmc1_clk 3.47 2.09 ns
rising clock edge
MMC7 t
su(DATxV-CLKIH)
Setup time, mmc1_datx valid before 2.13 2.41 ns
mmc1_clk rising clock edge
MMC8 t
h(CLKIH-DATxIV)
Hold time, mmc1_datx valid after mmc1_clk 3.47 2.09 ns
rising clock edge
MMC/SD/SDIO Interface 2
MMC3 t
su(CMDV-CLKIH)
Setup time, mmc2_cmd valid before 2.88 3.23 ns
mmc2_clk rising clock edge
MMC4 t
h(CLKIH-CMDIV)
Hold time, mmc2_cmd valid after mmc2_clk 2.90 1.46 ns
rising clock edge
MMC7 t
su(DATxV-CLKIH)
Setup time, mmc2_datx valid before 2.88 3.23 ns
mmc2_clk rising clock edge
MMC8 t
h(CLKIH-DATxIV)
Hold time, mmc2_datx valid after mmc2_clk 2.90 1.46 ns
rising clock edge
MMC/SD/SDIO Interface 3
MMC3 t
su(CMDV-CLKIH)
Setup time, mmc3_cmd valid before 3.38 3.41 ns
mmc3_clk rising clock edge
MMC4 t
h(CLKIH-CMDIV)
Hold time, mmc3_cmd valid after mmc3_clk 2.83 1.46 ns
rising clock edge
MMC7 t
su(DATxV-CLKIH)
Setup time, mmc3_datx valid before 3.38 3.41 ns
mmc3_clk rising clock edge
MMC8 t
h(CLKIH-DATxIV)
Hold time, mmc3_datx valid after mmc3_clk 2.83 1.46 ns
rising clock edge
(1) Timing parameters are referred to output clock specified in Table 6-141.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-141.
(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
Table 6-141. MMC/SD/SDIO Switching Characteristics Standard MMC Mode and MMC Identification
Mode
(1)(2)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
MMC Identification Mode
MMC1 t
c(clk)
Cycle time 2500 ns
MMC2 t
W(clkH)
Typical pulse duration, output clk high X
(3)
*PO
(4)
ns
MMC2 t
W(clkL)
Typical pulse duration, output clk low Y
(5)
*PO
(4)
ns
t
dc(clk)
Duty cycle error, output clk 2604.17 ns
t
j(clk)
Jitter standard deviation 200 ps
Standard MMC Mode
MMC1 t
c(clk)
Cycle time 2500 ns
MMC2 t
W(clkH)
Typical pulse duration, output clk high X
(3)
*PO
(4)
ns
MMC2 t
W(clkL)
Typical pulse duration, output clk low Y
(5)
*PO
(4)
ns
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(2) The jitter probability density can be approximated by a Gaussian function.
(3) The X parameter is defined as shown below.
(4) PO = output clk period in ns.
(5) The Y parameter is defined as shown below.
202 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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