Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 6-145. MMC/SD/SDIO Timing Requirements High-Speed SD Mode
(1)(2)(3)
(continued)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
HSSD7 t
su(DATxV-CLKIH)
Setup time, mmc1_datx valid before mmc1_clk rising 5.61 ns
clock edge
HSSD8 t
h(CLKIH-DATxIV)
Hold time, mmc1_datx valid after mmc1_clk rising 2.28 ns
clock edge
MMC/SD/SDIO Interface 2
HSSD3 t
su(CMDV-CLKIH)
Setup time, mmc2_cmd valid before mmc2_clk rising 5.61 ns
clock edge
HSSD4 t
h(CLKIH-CMDIV)
Hold time, mmc2_cmd valid after mmc2_clk rising 2.28 ns
clock edge
HSSD7 t
su(DATxV-CLKIH)
Setup time, mmc2_datx valid before mmc2_clk rising 5.61 ns
clock edge
HSSD8 t
h(CLKIH-DATxIV)
Hold time, mmc2_datx valid after mmc2_clk rising 2.28 ns
clock edge
MMC/SD/SDIO Interface 3
HSSD3 t
su(CMDV-CLKIH)
Setup time, mmc3_cmd valid before mmc3_clk rising 5.61 ns
clock edge
HSSD4 t
h(CLKIH-CMDIV)
Hold time, mmc3_cmd valid after mmc3_clk rising 2.28 ns
clock edge
HSSD7 t
su(DATxV-CLKIH)
Setup time, mmc3_datx valid before mmc3_clk rising 5.61 ns
clock edge
HSSD8 t
h(CLKIH-DATxIV)
Hold time, mmc3_datx valid after mmc3_clk rising 2.28 ns
clock edge
Table 6-146. MMC/SD/SDIO Switching Characteristics High-Speed SD Mode
(1)(2)
NO. PARAMETER 1.8 V, 3.3 V UNIT
MIN MAX
High-Speed SD Mode
HSSD1 t
c(clk)
Cycle time 20.83 ns
HSSD2 t
W(clkH)
Typical pulse duration, output clk high X
(3)
*PO
(4)
ns
HSSD2 t
W(clkL)
Typical pulse duration, output clk low Y
(5)
*PO
(4)
ns
t
dc(clk)
Duty cycle error, output clk 1041.67 ps
t
j(clk)
Jitter standard deviation 200 ps
MMC/SD/SDIO Interface 1
t
r(clk)
Rise time, output clk 3 ns
t
f(clkH)
Fall time, output clk 3 ns
t
r(clkL)
Rise time, output data 3 ns
t
f(clk)
Fall time, output data 3 ns
HSSD5 t
d(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to mmc1_cmd 3.72 14.11 ns
transition
HSSD6 t
d(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to mmc1_datx 3.72 14.11 ns
transition
MMC/SD/SDIO Interface 2
t
r(clk)
Rise time, output clk 3 ns
t
f(clkH)
Fall time, output clk 3 ns
t
r(clkL)
Rise time, output data 3 ns
t
f(clk)
Fall time, output data 3 ns
(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(2) The jitter probability density can be approximated by a Gaussian function.
(3) The X parameter is defined as shown in Table 6-147.
(4) PO = output clk period in ns.
(5) The Y parameter is defined as shown in Table 6-148.
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 205
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