Datasheet

jtag_tck
jtag_tdi
jtag_tms
jtag_rtck
jtag_tdo
JA1
JA2 JA3
JA4
JA5 JA6
JA7 JA8
JA10JA9
JA11
030-114
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-160. JTAG Switching Characteristics Adaptive Clock Mode
(1)
1.8 V 3.3 V
NO. PARAMETER MIN MAX MIN MAX UNIT
JA1 t
c(rtck)
Cycle time 20 20 ns
JA2 t
w(rtckL)
Typical pulse duration, jtag_rtck low 10 10 ns
JA3 t
w(rtckH)
Typical pulse duration, jtag_rtck high 10 10 ns
t
dc(rtck)
Duty cycle error, jtag_rtck -2500 2500 -2500 2500 ps
t
j(rtck)
Jitter standard deviation 33.33 33.33 ps
t
R(rtck)
Rise time, jtag_rtck 4 4 ns
t
F(rtck)
Fall time, jtag_rtck 4 4 ns
JA11 t
d(rtckL-tdoV)
Delay time, jtag_rtck low to jtag_tdo valid -14.6 14.6 -14.6 14.6 ns
t
R(tdo)
Rise time, jtag_tdo, 4 4 ns
t
F(tdo)
Fall time, jtag_tdo 4 4 ns
(1) The jitter probability density can be approximated by a Gaussian function.
Figure 6-74. JTAG Interface Timing Adaptive Clock Mode
214 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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