Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
mm_fsusb2_r 5 IO
xdp
E18 etk_d12 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_dir 3 I
gpio_26 4 IO
D20 etk_d13 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_nxt 3 I
gpio_27 4 IO
mm_fsusb2_r 5 IO
xdm
D19 etk_d14 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_ 3 IO
data0
gpio_28 4 IO
mm_fsusb2_r 5 IO
xrcv
D18 etk_d15 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
hsusb2_ 3 IO
data1
gpio_29 4 IO
mm_fsusb2_t 5 IO
xse0
M2 ddr_padref 0 A VDDS 1.8V
J8, J10, VDD_CORE 0 PWR 1.2V
J12, J14,
J16, K9,
K11, K13,
K15, L8,
L10, L12,
L14, M7,
M9, M11,
M13, M15,
N8, N10,
N12, N14,
P7, P9,
P11, P13,
P15, R8,
R10, R12,
R14
L17 VDDS_SRA 0 PWR 1.8V
M_MPU
J6 VDDS_SRA 0 PWR 1.8V
M_CORE_B
G
M17 CAP_VDD_S 0 PWR 1.2V
RAM_MPU
K6 CAP_VDD_S 0 PWR 1.2V
RAM_CORE
K17 VDDS_DPLL 0 PWR 1.8V
_MPU_USBH
OST
F11 VDDS_DPLL 0 PWR 1.8V
_PER_CORE
F7 VDDA3P3V_ 0 PWR 3.3V
USBPHY
D7 VDDA1P8V_ 0 PWR 1.8V
USBPHY
E7 CAP_VDDA1 0 PWR 1.2V
P2LDO_USB
PHY
Copyright © 2009–2013, Texas Instruments Incorporated Terminal Description 49
Submit Documentation Feedback
Product Folder Links: AM3517 AM3505