Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 2-5. External Memory Interfaces - SDRC Signals Description (continued)
SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
sdrc_d27 SDRAM data bit 27 IO C3 Y4
sdrc_d28 SDRAM data bit 28 IO C2 AA2
sdrc_d29 SDRAM data bit 29 IO D2 AA3
sdrc_d30 SDRAM data bit 30 IO B1 AA4
sdrc_d31 SDRAM data bit 31 IO C1 AB2
sdrc_ba0 SDRAM bank select 0 O A12 L4
sdrc_ba1 SDRAM bank select 1 O C13 K5
sdrc_ba2 SDRAM bank select 2 O D13 J5
sdrc_a0 SDRAM address bit 0 O A11 M3
sdrc_a1 SDRAM address bit 1 O B11 M4
sdrc_a2 SDRAM address bit 2 O C11 M5
sdrc_a3 SDRAM address bit 3 O D11 N3
sdrc_a4 SDRAM address bit 4 O E11 N2
sdrc_a5 SDRAM address bit 5 O A10 N4
sdrc_a6 SDRAM address bit 6 O B10 P3
sdrc_a7 SDRAM address bit 7 O C10 P2
sdrc_a8 SDRAM address bit 8 O D10 P1
sdrc_a9 SDRAM address bit 9 O E10 P4
sdrc_a10 SDRAM address bit 10 O A9 R1
sdrc_a11 SDRAM address bit 11 O B9 R2
sdrc_a12 SDRAM address bit 12 O A8 R3
sdrc_a13 SDRAM address bit 13 O B8 R4
sdrc_a14 SDRAM address bit 14 O D8 T2
sdrc_ncs0 Chip select 0 O E13 J4
sdrc_ncs1 Chip select 1 O A14 K4
sdrc_clk Clock O A13 L1
sdrc_nclk Clock Invert O B13 L2
sdrc_cke0 Clock Enable 0 O D14 K3
sdrc_nras SDRAM Row Access O C14 K1
sdrc_ncas SDRAM column address O E14 L3
strobe
sdrc_nwe SDRAM write enable O B14 K2
sdrc_dm0 Data Mask 0 O C21 F4
sdrc_dm1 Data Mask 1 O B15 J2
sdrc_dm2 Data Mask 2 O E8 T4
sdrc_dm3 Data Mask 3 O D1 AB3
sdrc_strben0 PCB layout trace loop 0 A A19 F2
pin 0
sdrc_strben_dly0 PCB layout trace loop 0 A A18 F1
pin 1
sdrc_strben1 PCB layout trace loop 1 A A5 W1
pin 0
sdrc_strben_dly1 PCB layout trace loop 1 A A4 W2
pin 1
sdrc_odt On-die termination output O C8 T1
for sdrc_ncs0 only
sdrc_dqs0p Data Strobe 0 IO B20 E2
sdrc_dqs0n Data Strobe 0 IO A20 E1
sdrc_dqs1p Data Strobe 1 IO B17 H2
60 Terminal Description Copyright © 2009–2013, Texas Instruments Incorporated
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