Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 2-5. External Memory Interfaces - SDRC Signals Description (continued)
SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
sdrc_dqs1n Data Strobe 1 IO A17 H1
sdrc_dqs2p Data Strobe 2 IO A6 U1
sdrc_dqs2n Data Strobe 2 IO B6 U2
sdrc_dqs3p Data Strobe 3 IO A2 Y1
sdrc_dqs3n Data Strobe 3 IO B2 Y2
ddr_padref Impedance control for A B12 M2
DDR2 output. This pin
must be connected to
ground via a 50-ohm (±
2%) resistor.
VREFSSTL VREFSSTL is .5 * VDDS IO F14 L5
= 0.9V for DDR data
PHY0 reference voltage
input
2.4.2 Video Interfaces
Table 2-6. Video Interfaces - CCDC Signals Description
SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4] SYSTEM MUX
MODE
(1)
ccdc_pclk CCDC pixel clock IO AD2 AB21 mode0
ccdc_field CCDC field ID signal IO AD1 AA21 mode0
ccdc_hd CCDC horizontal IO AE2 Y21 mode0
sync
ccdc_vd CCDC vertical sync IO AD3 Y22 mode0
ccdc_wen CCDC write enable I AE3 W21 mode0
ccdc_data0 CCDC data bit 0 I AD4 W22 mode0
ccdc_data1 CCDC data bit 1 I AE4 W20 mode0
ccdc_data2 CCDC data bit 2 I AC5 V21 mode0
ccdc_data3 CCDC data bit 3 I AD5 V19 mode0
ccdc_data4 CCDC data bit 4 I AE5 V22 mode0
ccdc_data5 CCDC data bit 5 I Y6 U20 mode0
ccdc_data6 CCDC data bit 6 I AB6 V20 mode0
ccdc_data7 CCDC data bit 7 I AC6 U19 mode0
ccdc_data8 CCDC data bit 8 I AE6 U21 mode1
ccdc_data9 CCDC data bit 9 I AD6 U22 mode1
ccdc_data10 CCDC data bit 10 I Y7 T19 mode1
ccdc_data11 CCDC data bit 11 I AA7 T20 mode1
ccdc_data12 CCDC data bit 12 I AB7 T21 mode1
ccdc_data13 CCDC data bit 13 I AC7 R22 mode1
ccdc_data14 CCDC data bit 14 I AD7 T22 mode1
ccdc_data15 CCDC data bit 15 I AE7 R20 mode1
(1) See Multiplexing Characteristics table for more information.
Table 2-7. Video Interfaces - DSS Signals Description
SIGNAL NAME[1] DESCRIPTION [2] TYPE [3] ZCN BALL [4] ZER BALL [4]
dss_pclk LCD Pixel Clock O AE23 B22
dss_hsync LCD Horizontal O AD22 B21
Synchronization
dss_vsync LCD Vertical O AD23 B20
Synchronization
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