Datasheet

MPU
Core
Periph1
vdd_core domain
DPLL_MPU
LDO
in 1.8 V
out 1.2 V
Dual Video DAC
SRAM2
ARRAY
SRAM 2 LDO
0 V/1.0 V/1.2 V
SRAM1
ARRAY
SRAM 1 LDO
0 V/1.0 V/1.2 V
DPLL_CORE
LDO
in 1.8 V
out 1.2 V
DPLL4
LDO
in 1.8 V
out 1.2 V
LDO3
1.0 V/1.2 V
vdds
Periph2
DPLL5
LDO
in 1.8 V
out 1.2 V
BandGap
BCK
MEM
vss
DLL/DCDL
HSDIVIDER
LDO
HSDIVIDER
LDO
cap_vdd_sram_core
tv_ref
(for capacitor)
vssa_dac
vdds_dpll_mpu_usbhost
vddshv
Device
vdd_core
vdds_dpll_per_core
vdda_dac
030-003
VDDSHV
VDDS
AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
The following diagram illustrates the power domains:
Figure 3-1. AM3517/05 Voltage Domains
Copyright © 2009–2013, Texas Instruments Incorporated Electrical Characteristics 83
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