Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
3.5 Power-up and Power-down
This section provides the timing requirements for the AM3517/05 hardware signals.
3.5.1 Power-up Sequence
The following steps give an example of power-up sequence supported by the AM3517/05.
1. IO 1.8V supply (VDDS), Band-gap and LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU)
and oscillator supply (VDDSOSC) should come up first to a stable state.
2. IO 3.3V (VDDSHV) supply should be ramped up next to a stable state.
3. Core (VDD_CORE) supply follows next to a stable state.
4. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) and 1.8 V complex
IO supplies (VDDA_DAC, VDDA1P8V_USBPHY) should be ramped up next to a stable state.
5. Finally, 3.3 V complex IO (VDDA_3P3V_USBPHY) should be ramped up.
6. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the
sys_32k and sys_xtalin clocks are stable.
Note: In VDDSHV 1.8 V operation mode, VDDSHV can be grouped and powered up together with VDDS,
VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU and VDDSOSC.
88 Electrical Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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