Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 4-3. 32-kHz Input Clock Source Electrical Characteristics
PARAMET DESCRIPTION MIN TYP MAX UNIT
ER
f Frequency, sys_32k 32.768 kHz
C
i
Input capacitance 0.45 pF
R
i
Input resistance 0.25 10
6
GΩ
Table 4-4 details the input requirements of the 32-kHz input clock.
Table 4-4. 32-kHz Input Clock Source Timing Requirements
(1)
PARAMETE DESCRIPTION MIN TYP MAX UNIT
R
1 / t
c(32k)
Frequency, sys_32k 32 kHz
t
R(32k)
Rise transition time, sys_32k 20 ns
t
F(32k)
Fall transition time, sys_32k 20 ns
t
J(32k)
Frequency stability, sys_32k +/-200 ppm
(1) See Electrical Characteristics for Standard LVCMOS IOs part for sys_32k V
IH
/V
IL
parameters.
Table 4-5. 48-MHz, 54-MHz, or up to 59-MHz Input Clock Source Electrical Characteristics
NAME DESCRIPTION MIN MAX UNIT
f Frequency , sys_altclk 48, 54, or up to 59 MHz
C
i
Input capacitance 0.74 pF
R
i
Input resistance 0.25 10
6
GΩ
Table 4-6 details the input requirements of the 48- or 54-MHz input clock.
Table 4-6. 48-MHz, 54-MHz, or up to 59-MHz Input Clock Source Timing Requirements
(1) (2)
PARAMETER DESCRIPTION MIN MAX UNIT
1 / t
c(sys_altclk)
Frequency, sys_altclk 48, 54, or up to 59 MHz
t
w(sys_altclk)
Duty cycle 45 60 %
t
j(sys_altclk)
Jitter -1 1 %
t
r(sys_altclk)
Rise transition time 10 ns
t
f(sys_altclk)
Fall transition time 10 ns
f
t(sys_altclk)
Frequency tolerance -50 50 ppm
(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300
period samples. The sinusoidal noise is added on top of the vdds supply voltage.
(2) See Section 3, Electrical Characteristics, for sys_altclk V
IH
/V
IL
parameters.
94 Clock Specifications Copyright © 2009–2013, Texas Instruments Incorporated
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