Datasheet

DPLL_MPU

DPLL_CORE

DLL

DPLL5

DPLL4

VDDS_DPLL_MPU_USBHOST

VDDS_DPLL_PER_CORE

Noise Filter

030-017

AM3517, AM3505

www.ti.com

SPRS550E –OCTOBER 2009–REVISED MARCH 2013

4.4.2 DPLL Noise Isolation

The DPLL requires dedicated power supply pins to isolate the core analog circuit from the switching noise

generated by the core logic that can cause jitter on the clock output signal. Guard rings are added to the

cell to isolate it from substrate noise injection.

The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the

supply rails. The maximum input noise level allowed is 30 mV

for frequencies below 1 MHz.

Figure 4-7 illustrates an example of a noise filter.

Figure 4-7. DPLL Noise Filter

Table 4-11 specifies the noise filter requirements.

Table 4-11. DPLL Noise Filter Requirements

NAME MIN TYP MAX UNIT

Filtering capacitor 100 nF

(1) The capacitors must be inserted between power and ground as close as possible.

(2) This circuit is provided only as an example.

(3) The filter must be located as close as possible to the device.

(4) No filtering required if noise is below 10 mV

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