Datasheet

Manchester Decoding
Comparator Unit
AMC1210
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Manchester signaling is a method of encoding a data signal in such a way that it can be retrieved without the
need of a separate clock line. When configured in Mode 2, the AMC1210 can translate a Manchester-encoded
signal on the INx pin into a clock signal and a data signal. An automatic calibration is continuously performed to
optimize the decoding of the data.
The calibration mechanism follows this sequence:
1. The modulator data is sampled at the frequency of the system clock (CLK).
2. The number of CLK cycles between transitions is counted and recorded for 1024 consecutive transitions.
3. The resulting array will have a '1' in the bit location that corresponds to the number of CLK cycles counted
between transitions. For example, the sequence shown in Table 8 means that there was at least one
instance where three and four, as well as seven and eight, CLK cycles occurred between two transitions.
This array is stored in the bits MS10 – MS0 in the Control Parameter Register .
4. An algorithm looks for a group of zeros that has ones before and after it. If this pattern is not found, the bits
MALx and MAFx in the Status Register are set high.
5. If the algorithm is successful, it will use the location of the first '0' as the number of CLK cycles needed to
determine the frequency and which transitions are valid in the Manchester code.
6. The algorithm starts over from Step 2 automatically.
Table 8. Example Control Parameter Register
VALUE 0 0 0 1 1 0 0 1 1 0 0
BIT MS10 MS9 MS8 MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0
CLK
11 10 9 8 7 6 5 4 3 2 1
CYCLES
The MALx bit shows the status of the previous Manchester decoder calibration cycle. If it is high, the decoder
calibration has failed on the previous calibration cycle. The MAFx bit shows if any failures have occurred since
the last read of the Status Register . Any MALx failure will cause MAFx to go high. MAFx is reset to low when the
Status Register is read.
The decoding procedure is performed continuously when the AMC1210 is configured for Modulator Mode 2. Note
that the CLK frequency must be at least six times the Manchester data rate for the decoder to perform properly.
An independent comparator unit allows the user to monitor input conditions with a fast settling time without
sacrificing input measurement resolution. The filter of the comparator unit is similar to the sinc filter unit, with
OSR values ranging continuously between 1 and 32. Setting the OSR to 32, a maximum 15-bit output width of
32,768 can be achieved. The output of the filter is compared with two programmed threshold levels to detect
over- and under-value conditions. These threshold levels are programmed in the high and low level Threshold
Registers for each individual filter module. When an over- or under-value condition occurs, it signals the interrupt
unit to set an interrupt signal and store the conditions in the Interrupt Register . The Interrupt Register can then be
polled to see which condition caused the interrupt signal. It is not possible to read out the value of the
comparator filter.
This filter, together with the comparators, is generally used to detect over-currents. It is necessary to decide on
an OSR given the desired resolution/settling time combination. This programming will be discussed in more detail
in the Applications Information section.
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