Datasheet
Control Register (address 0x19)
Pattern Register (address 0x1A)
AMC1210
SBAS372D – APRIL 2006 – REVISED MAY 2009 ..............................................................................................................................................................
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The Control Register controls the signal pattern generator and the interrupt and acknowledge pin behavior. It
specifies the interrupt and acknowledge pin polarities, the master interrupt enable and the signal pattern
generator length. Table 20 shows the Control Register.
Table 20. Control Register
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AP IP MIE – – – PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
'0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0'
RW RW RW R R R RW RW RW RW RW RW RW RW RW RW
BIT POSITION BIT DESCRIPTION
Acknowledge polarity for pin ACK.
15 AP 0: New data is signaled with a '1' on the pin ACK
1: New data is signaled with a '0' on the pin ACK
Interrupt polarity for pin INT.
14 IP 0: An interrupt is signaled with a positive transition on the pin INT
1: An interrupt is signaled with a negative transition on the pin INT
Master interrupt enable.
0: Interrupt pin and interrupt flags are blocked (interrupt pin INT always inactive).
13 MIE
1: Interrupt pin and interrupt flags are not blocked and can be set and reset (if individually
enabled).
12 – 10 – Unused. Always read '0'.
Pattern count.
9 – 0 PC9 – PC0
Defines the length of the shift register for the signal generator
The shift register of the signal generator is written through the Pattern Register. Each time this register is written,
the shift register is shifted 16 bits upwards and the written data is stored in the 16 LSBs of the shift register. The
Pattern Register is a write-only register; a read always returns 0x0000. Table 21 describes the Pattern Register.
Table 21. Pattern Register
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
'0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0'
W W W W W W W W W W W W W W W W
BIT POSITION BIT DESCRIPTION
15 – 0 SP15 – SP0 Shift register pattern.
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