Datasheet
Clock Divider Register (address 0x1B)
AMC1210
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.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009
The Clock Divider Register sets up the signal generator, the modulator clock division and the signal generator
clock. Table 22 shows the Clock Divider Register.
Table 22. Clock Divider Register
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– – – HBE MFE SGE PCAL SCS1 SCS0 MD2 MD1 MD0 SD3 SD2 SD1 SD0
'0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0' '0'
R R R RW RW RW RW RW RW RW RW RW RW RW RW RW
BIT POSITION BIT DESCRIPTION
15 – 13 – Unused. Always read '0'.
Signal Generator High-Current Output.
12 HBE 0: The high current option for pins PWM1 and PWM2 is disabled
1: The PWM1 and PWM2 outputs are in High Current Mode
Master Filter Enable. Functionally AND'ed with bit FEN in the Sinc Filter Parameter
Register.
11 MFE
0: Sinc filter units of all filter modules are disabled.
1: Sinc filter units can be enabled if bit FEN is '1'.
Signal Generator enable.
10 SGE 0: Signal generator is disabled
1: Signal generator is enabled
Start of phase correction.
Writing a '1' to this bit starts the phase calibration. Reading this bit shows the phase
9 PCAL calibration status:
1: The phase calibration is performing
0: No phase calibration is performing
Signal generator Control Select (necessary for Phase Calibration and Demodulation on the
selected channel).
00: The phase calibration is performed on filter module 1
8 – 7 SCS1 – SCS0
01: The phase calibration is performed on filter module 2.
10: The phase calibration is performed on filter module 3.
11: The phase calibration is performed on filter module 4.
Modulator clock divider.
6 – 4 MD2 – MD0
The coding is equal to the first eight codes in SD; see below.
Signal generator clock divider.
0000: Clock divider is off, outgoing clock equals incoming clock
0001: Outgoing clock is divided by 2
0010: Outgoing clock is divided by 3
0011: Outgoing clock is divided by 4
0100: Outgoing clock is divided by 5
0101: Outgoing clock is divided by 6
0110: Outgoing clock is divided by 7
3 – 0 SD3 – SD0 0111: Outgoing clock is divided by 8
1000: Outgoing clock is divided by 9
1001: Outgoing clock is divided by 10
1010: Outgoing clock is divided by 11
1011: Outgoing clock is divided by 12
1100: Outgoing clock is divided by 13
1101: Outgoing clock is divided by 14
1110: Outgoing clock is divided by 15
1111: Outgoing clock is divided by 16
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