Datasheet
Example 2: AMC1210 Configuration with 8kHz Carrier Frequency and 32MHz System Clock Frequency
Motor control loop frequency + f
CARRIER
+ 8kHz
(3)
f
CLK
+ 32MHz
(4)
f
CARRIER
+
f
CLK
ǒ
N
CDiv
@ N
PAT
Ǔ
+
32MHz
ǒ
N
CDiv
@ 1000
Ǔ
(5)
CLK_Divider +
f
CLK
ǒ
f
CARRIER
@ N
PAT
Ǔ
+
32MHz
(
8kHz @ 1000
)
+ 4
(6)
ENOB
OSR
1
10
100 1000
16
14
12
10
8
6
4
2
0
Sinc
1
Sinc
2
Sinc
3
Sincfast
ADS1205
f =(f SOSR ISOR)/N×
MODULATOR CARRIER INT
×
(7)
AMC1210
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.............................................................................................................................................................. SBAS372D – APRIL 2006 – REVISED MAY 2009
The carrier frequency is generated using the signal generator, which uses the CLK signal for timing. In order to
achieve optimal resolution on the carrier signal, it is recommended to use the largest number of bits possible, up
to 1024, for a single cycle of the carrier signal. In this example, the length of the signal generator (PC9 – PC0 in
the Control Register ) was chosen to be 1000. This length means the carrier frequency will be:
Now the Clk_divider value for the signal generator (SD3 – SD0 in the Clock Divider Register ) can be calculated:
Therefore, the user can generate a carrier frequency of 8kHz using a CLK speed of 32MHz, and programming
bits PC9 – PC0 to 999 (1000 – 1) and bits SD3 – SD0 to 3 (4 – 1).
The next matter of importance is to determine the optimal speed versus resolution tradeoff on the modulator.
Figure 24 shows the tradeoff in performance for speed on the ADS1205 modulator. A higher OSR can provide
increased ENOB (effective number of bits); however, it requires more data from the converter, resulting in an
increased filter delay.
Figure 24. Effective Number of Bits vs Oversampling Ratio (ADS1205)
For maximum resolution, it is best to run the modulator as fast as possible. The speed of the modulator
determines what oversampling ratio is needed on the sinc filter and the integrator. In order to synchronize to the
motor control loop, the modulator must be decimated down by an integer divisor of the modulator frequency. This
relationship is given in Equation 7 .
Where N
INT
is the number of carrier signal cycles that will be integrated over. This value is usually set to 1; refer
to the application note Using the AMC1210 in Resolver Motor Control Systems (SBAA144) for more detail.
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