Datasheet

MODULATOR INPUT MODES
TIMING CHARACTERISTICS
Mode0
CLKx
INx
t
su1
t
h1
t
w1
t
w2
CLKx
INx
Mode1
t
su2
t
su2
t
h2
t
h2
t
w3
t
w4
Modulatorinternalclock
Modulatorinternaldata
Mode2
(Manchester-encodedbitstream)
1 0 1 1
0
0 1
1 1
t
w6
t
w5
INx
CLKx
INx
Mode3
(CLKxisdrivenexternally)
t
w7
t
w8
t
su3
t
h3
CLKx
INx
CLK
t
w11
Mode3
(CLKxisgeneratedbyAMC1210)
t
d11
t
w12
t
d2
t
w10
t
w9
t
su4
t
h4
AMC1210
SBAS372D APRIL 2006 REVISED MAY 2009 ..............................................................................................................................................................
www.ti.com
Over recommended operating free-air temperature range at 40 ° C to +125 ° C, DVDD = +5V, CVDD = +5V, and BVDD = +2.7V, unless
otherwise noted.
PARAMETER MIN MAX UNIT
t
w1
Mode 0 clock period CLKx 45 1/64th of CLK period ns
t
w2
Mode 0 clock high time CLKx 10 t
w1
10 ns
t
su1
Setup time from data valid to CLKx high 5 ns
t
h1
Hold time from CLKx high to data invalid 5 ns
t
w3
Mode 1 clock period CLKx 90 1/128th of CLK period ns
t
w4
Mode 1 clock high time CLKx 20 t
w3
10 ns
t
su2
Setup time from data valid to CLKx high or low 5 ns
t
h2
Hold time from CLKx high or low to data invalid 5 ns
t
w5
Mode 2 data width INx 45 ns
t
w6
Mode 2 data pulse width INx 22 ns
t
w7
Mode 3 clock period CLKx 22 1/32nd of CLK period ns
t
w8
Mode 3 clock high time CLKx 5 t
w7
5 ns
t
su3
Setup time from data valid to any CLKx high 5 ns
t
h3
Hold time from any CLKx high to data invalid 5 ns
t
w9
System clock period CLK 11 ns
10
6
t
w10
System clock high time CLK 3 t
w9
3 ns
t
w11
Mode 3 generated clock period CLK
x
t
w9
t
w9
× MD control bits ns
t
w12
Mode 3 generated high time CLKx t
w10
2 t
w10
+ 2 ns
t
d1
Delay from system clock CLK high to generated CLKx high 0 3 ns
t
d2
Delay from system clock CLK low to generated CLKx low 0 3 ns
t
su4
Setup time from data valid to any CLKx high 5 ns
t
h4
Hold time from any CLKx high to data invalid 5 ns
Figure 1. Modulator Input Mode Timing
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Product Folder Link(s): AMC1210