Datasheet
AMC6821-Q1
www.ti.com
...................................................................................................................................................................................................... SBAS475 – JUNE 2009
Configuration Register 2 (Address 0x01, Value After Power-On Reset = 0x3D)
BIT NAME R/W DEFAULT DESCRIPTION
Reset bits. RST = 1 resets the device. Self-clears after reset. Always read '0'. Power-on
7 RST R/W 0 default = 0. Reset is immediate on rising edge of SCLK of data LSB with no
acknowledge.
LPSV enable bit. Power-on default = 0. When LPSVIE = 1, the LPSV interrupt is enabled
6 PSVIE R/W 0 and an interrupt is generated when LPSV = 1. When LPSVIE = 0, LPSV is disabled and
LPSV = 1 does not cause an interrupt.
Remote temperature interrupt enable bit. When RTIE = 1, the remote temperature
interrupt is enabled and RTO = 1 causes an interrupt. When RTIE = 0, the remote
5 RTOIE R/W 1
temperature interrupt is disabled and RTO = 1 does not generate an interrupt. Power-on
default = 1, except when a remote sensor failure is detected at power-on.
Local temperature interrupt enable bit. Power-on default = 1. When LTIE = 1, the local
4 LTOIE R/W 1 temperature interrupt is enabled and LTO = 1 causes an interrupt. When LTIE = 0, the
local temperature interrupt is disabled and LTO = 1 does not generate an interrupt.
Remote sensor failure interrupt enable bit. Power-on default = 1. When RTFIE = 1, the
remote sensor failure interrupt is enabled and RTF = 1 causes an interrupt through the
3 RTFIE R/W 1
SMBALERT pin. When RTFIE = 0, the remote sensor failure interrupt is disabled and
RTF = 1 does not generate an interrupt through the SMBALERT pin.
Setting this bit to '1' enables the TACH input. Clearing ('0') disables the TACH input and
2 TACH-EN R/W 1 freezes the counter. Power-on default = 1. If TACH-EN is cleared, TACH-MODE must be
set ('1').
When the TACH-MODE bit is cleared ('0'), the PWM-Out pin is forced ON during RPM
measurement, and internal correction circuitry is enabled to correct the error caused by
this extra duty cycle. Making TACH-MODE = 0 for the fans that are switched ON/OFF
directly by the PWM requires PWM ON to provide TACH pulses. In the software RPM
mode, the PWM-Out is forced to 30% duty cycle if the calculated duty cycle is less than
30% when TACH-MODE = 0. In all other modes the PWM-Out is forced to 0% if the
1 TACH-MODE R/W 0 calculated duty cycle is less than 7%. When the TACH mode is set ('1'), the internal
correction circuit is disabled and PWM-Out is not forced ON. Instead, the PWM-Out pin
is completely controlled by the value of the DCY register, just as in normal operation.
Setting the TACH-MODE bit ('1') when the fans can provide TACH pulses output
regardless the status of the PWM-Out pin. The TACH mode must be '1' for any fan
which is powered directly by dc power, such as a four-wire fan. Power-on default = 0.
(See the TACH-DATA Register section for details.)
Setting this bit to '1' enables the PWM-Out pin. Clearing ('0') disables the PWM-Out pin
0 PWM-EN R/W 1
(H-Z). Power-on default = 1.
Configuration Register 3 (Address 0x3F, Value After Power-On Reset = 0x82)
BIT NAME R/W DEFAULT DESCRIPTION
Setting this bit to '1' enables the fan to run at full-speed when the THERM pin as
an output) is asserted low. This configuration allows the system to be run in
performance mode. Clearing this bit to '0' disables the fan from running at
7 THERM-FAN-EN R/W 1 full-speed whenever the THERM pin (as an output) is asserted low. This
configuration allows the system to run in silent mode. Note that this bit has no
effect whenever THERM is pulled low as an input. The fan always runs at full
speed when the THERM pin is pulled low as an input. Power-on default = 1.
6 Reserved R 0 Read-back '0'.
5 Reserved R 0 Read-back '0'.
4 Reserved R 0 Read-back '0'.
3 Part Revision Number R 0 0, bit 3 (MSB) of 4-bit revision number.
2 Part Revision Number R 0 0, bit 2 of revision number.
1 Part Revision Number R 1 0, bit 1 of revision number.
0 Part Revision Number R 0 0, bit 0 (LSB) of revision number.
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