AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors Check for Samples: AMC7812 FEATURES DESCRIPTION • 12, 12-Bit DACs with Programmable Outputs: – 0V to 5V – 0V to 12.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS At TA = –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AVCC = +15V, AGND = DGND = 0V, IOVDD = 2.7V to 5.5V, internal 2.5V reference, and the DAC output span = 0V to 5V, unless otherwise noted.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AVCC = +15V, AGND = DGND = 0V, IOVDD = 2.7V to 5.5V, internal 2.5V reference, and the DAC output span = 0V to 5V, unless otherwise noted. AMC7812 PARAMETER TEST CONDITIONS MIN TYP MAX 2.495 2.5 2.505 UNIT INTERNAL REFERENCE Output voltage TA = +25°C, REF-OUT pin Output impedance 0.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AVCC = +15V, AGND = DGND = 0V, IOVDD = 2.7V to 5.5V, internal 2.5V reference, and the DAC output span = 0V to 5V, unless otherwise noted. AMC7812 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC REFERENCE INPUT Reference input voltage range Input current 1.2 VREF = 2.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AVCC = +15V, AGND = DGND = 0V, IOVDD = 2.7V to 5.5V, internal 2.5V reference, and the DAC output span = 0V to 5V, unless otherwise noted. AMC7812 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL LOGIC: All Except SCL, SDA, ALARM, and GPIO VIH Input high voltage VIL Input low voltage IOVDD = +5V 2.1 0.3 + IOVDD V IOVDD = +3.3V 2.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 FUNCTIONAL BLOCK DIAGRAM Single-Ended Single-Ended/ Differential ADC-REF-IN/CMP AMC7812 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 Reference (2.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 PIN DESCRIPTIONS (continued) PIN (QFN / HTQFP) NO. DESCRIPTION NAME 17 DAC-CLR-0 18 DAC5-OUT 19 DAC4-OUT 20 DAC3-OUT 21 AGND4 22 AGND3 23 AVCC2 24 DAC2-OUT 25 DAC1-OUT DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-0 pin enter a clear state, the DAC Latch is loaded with predefined code, and the output is set to the corresponding level.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com I2C-COMPATIBLE TIMING DIAGRAMS S Sr P S SDA tSU, STA tSU, DAT tBUF tHD, STA tHD, DAT tLOW SCL tSU, STO tHIGH tHD,STA tR tF S = START Condition Sr = Repeated START Condition P = STOP Condition = Resistor Pull-Up Figure 1. Timing for Standard and Fast Mode Devices on the I2C Bus TIMING CHARACTERISTICS: SDA and SCL for Standard and Fast Modes (1) At –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AGND = DGND = 0V, and IOVDD = 2.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Sr Sr P tFDA tRDA SDA tHD, DAT tSU, STA tHD, STA tSU, STO tSU, DAT SCL tFCL tRCL1(1) tHIGH tLOW tRCL1(1) tRCL tLOW tHIGH = Current Source Pull-Up = Resistor Pull-Up (1) Sr = Repeated START Condition P = STOP Condition First rising edge of the SCL signal after Sr and after each acknowledge bit. Figure 2.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com SPI TIMING DIAGRAMS t8 t10 t4 CS t1 t7 t3 SCLK t2 tR tF t5 SDI t6 Bit 23 Bit 1 -- Don’t Care Bit 0 Bit 23 = MSB Figure 3. SPI Single-Chip Write Operation t1 t7 t4 CS t1 SCLK t3 t2 tF t5 t6 Bit 22 Bit 23 SDI tR Bit 0 Bit 23 Read Command Bit 22 t9 SDO Bit 1 Bit 0 Any Command Bit 23 Bit 22 Bit 1 Bit 0 Data Read from the Register Selected in the Previous Read Operation Figure 4.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 TIMING CHARACTERISTICS: SPI Bus (1) (2) At –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AGND = DGND = 0V, and IOVDD = 3.0V to 5.5V, unless otherwise noted.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: DAC At +25°C, unless otherwise noted. LINEARITY ERROR vs CODE 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (LSB) DNL (LSB) DIFFERENTIAL LINEARITY ERROR vs CODE 1 0 −0.2 −0.4 −0.4 −0.6 −0.6 TA = −40°C Gain = 2 VREF = 2.5V, Internal −0.8 −1 0 −0.2 0 512 1024 1536 2048 Code 2560 3072 3584 TA = −40°C Gain = 2 VREF = 2.5V, Internal −0.8 −1 4096 0 512 1024 Figure 6. 0.8 0.8 0.6 0.6 0.4 0.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: DAC (continued) At +25°C, unless otherwise noted. LINEARITY ERROR vs CODE 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (LSB) DNL (LSB) DIFFERENTIAL LINEARITY ERROR vs CODE 1 0 −0.2 −0.4 −0.2 −0.4 −0.6 −0.6 TA = +25°C Gain = 5 VREF = 2.5V, Internal −0.8 −1 0 0 512 1024 1536 2048 Code 2560 3072 3584 TA = +25°C Gain = 5 VREF = 2.5V, Internal −0.8 −1 4096 0 512 1024 1536 Figure 12. 1 0.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: DAC (continued) At +25°C, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE 1 1 Ch0 Ch1 Ch2 Ch3 0.8 Ch8 Ch9 Ch10 Ch11 0.6 0.4 0.4 0.2 0.2 0 −0.2 −0.4 Ch3 Ch4 Ch5 −0.2 0 512 1024 1536 2048 Code 2560 3072 3584 TA = +25°C Gain = 2 VREF = 2.5V, Internal −0.8 −1 4096 0 512 1024 1536 Figure 18.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: DAC (continued) At +25°C, unless otherwise noted. GAIN ERROR vs SUPPLY GAIN ERROR vs SUPPLY 0.15 0.3 0.2 Gain Error (%FSR) 0.05 0 −0.05 0.1 0 −0.1 TA = +25°C Gain = 2 VREF = 2.5V, Internal −0.1 −0.15 4.5 6 7.5 9 10.5 12 AVCC (V) 13.5 15 16.5 −0.2 −0.3 18 12 13 14 Figure 24. OFFSET VOLTAGE 17 18 OFFSET VOLTAGE 35 Offset Error (mV) 1.4 1.6 1 1.2 0.8 0.4 0 0.2 -0.2 -0.6 -1 -0.8 0.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: DAC (continued) At +25°C, unless otherwise noted. OFFSET VOLTAGE vs SUPPLY VOLTAGE OFFSET VOLTAGE vs SUPPLY VOLTAGE 3 5 3 Offset Error (mV) Offset Error (mV) 2 1 0 −1 TA = +25°C Gain = 2 VREF = 2.5V, Internal Code = 020h −2 −3 4.5 6 7.5 9 10.5 12 13.5 15 16.5 −1 TA = +25°C Gain = 5 VREF = 2.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: DAC (continued) At +25°C, unless otherwise noted. SUPPLY CURRENT vs DAC CODE SUPPLY CURRENT vs TEMPERATURE 6.5 6 6.1 5.5 5.8 5 5.1 IVCC (mA) 4.7 4.4 4.5 4 4 All DAC Channels TA = +25°C Gain = 2 VREF = 2.5V, Internal 3.7 3.4 3 0 512 1024 1536 2048 Code 2560 3072 3584 Gain = 2 VREF = 2.5V, Internal Code = 800h 3.5 3 −40 4096 −25 −10 5 20 Figure 36.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: DAC (continued) At +25°C, unless otherwise noted. SETTLING TIME FALLING EDGE 2 16 1.5 Small Signal (LSB) 1 0.5 14 12 10 0 8 −0.5 6 −1 4 −1.5 2 −2 −3 0 3 6 9 12 Large Signal (V) TA = +25°C Gain = 2 VREF = 2.5V, Internal RL= 2KΩ, CL = 250pF DAC Out SS DAC Out LS CS 0 Time (µs) Figure 42.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: ADC At +25°C, unless otherwise noted. LINEARITY ERROR vs CODE 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (LSB) DNL (LSB) DIFFERENTIAL LINEARITY ERROR vs CODE 1 0 −0.2 −0.4 −0.8 −1 −0.4 TA = +25°C 0V to VREF Mode VREF = 2.5V, Internal Single−Ended Mode −0.6 0 512 1024 1536 2048 Code 2560 3072 3584 0 −0.2 TA = +25°C 0V to VREF Mode VREF = 2.5V, Internal Single−Ended Mode −0.6 −0.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: ADC (continued) At +25°C, unless otherwise noted. LINEARITY ERROR vs CODE 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 INL (LSB) DNL (LSB) DIFFERENTIAL LINEARITY ERROR vs CODE 1 0 −0.2 −0.4 −0.8 −1 0 512 1024 1536 2048 Code 2560 3072 3584 −0.2 −0.4 TA = +25°C 0V to (2 ⋅ VREF) Mode VREF = 2.5V, Internal Differential Mode −0.6 0 TA = +25°C 0V to (2 ⋅ VREF) Mode VREF = 2.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: ADC (continued) At +25°C, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE 1 0.8 0.8 0.6 0.6 INL Max 0.4 0.4 0.2 0.2 INL (LSB) INL (LSB) LINEARITY ERROR vs TEMPERATURE 1 0 −0.2 −0.4 0V to (2 ⋅ VREF) Mode VREF = 2.5V, Internal Single−Ended Mode INL Max 0 −0.2 −0.4 −0.6 −0.8 −1 −40 −25 −10 5 −0.6 0V to VREF Mode VREF = 2.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: ADC (continued) At +25°C, unless otherwise noted. OFFSET vs TEMPERATURE CONVERSION FREQUENCY 20 5 4 0V to VREF Mode 0V to (2 ⋅ VREF) Mode 972 Units VREF = 2.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: ADC (continued) At +25°C, unless otherwise noted. SUPPLY CURRENT vs CONVERSION RATE 50 8 COMBINED AVDD AND DVDD SUPPLY CURRENT TA = +25°C 864 Units 7 40 500 AIDD (mA)) Figure 67. 12 400 11.5 200 300 Frequency (kHz) 11 100 10.5 0 0 10 10 9 Auto Convert Mode Direct Mode With Nap Direct Mode Without Nap 9.5 0 Single Channel all DACs at code 800h 8.5 1 8 2 20 7.5 3 30 7 4 6.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: INTERNAL REFERENCE At +25°C, unless otherwise noted. OUTPUT VOLTAGE vs TEMPERATURE OUTPUT VOLTAGE vs SUPPLY 2.505 2.501 10 Units 2.503 Voltage Output (V) Voltage Output (V) 2.5005 2.501 2.499 2.5 2.4995 2.497 TA = +25°C 2.495 −40 −25 −10 5 20 35 50 65 80 95 2.499 2.7 110 125 3.1 3.5 3.9 TA (°C ) 4.3 4.7 5.1 5.5 AVDD (V) Figure 69. Figure 70.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS: TEMPERATURE SENSOR At +25°C, unless otherwise noted. LOCAL TEMPERATURE ERROR vs TEMPERATURE REMOTE TEMPERATURE ERROR vs TEMPERATURE 2.5 Local Temperature Error (°C ) Remote Temperature Error (°C ) 10 Units QFN Package 2 1.5 1 0.5 0 −0.5 −1 −1.5 −2 −2.5 −40 −25 −10 5 20 35 50 65 80 95 1.5 10 Units QFN Package Auto Conversion Mode Disabled 1 0.5 0 −0.5 −1 −1.5 −2 −2.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com THEORY OF OPERATION ADC OVERVIEW The AMC7812 has two analog-to-digital converters (ADCs): a primary ADC and a secondary ADC. The primary ADC features a 16-channel multiplexer, an on-chip track-and-hold, and a successive approximation register (SAR) ADC based on a capacitive digital-to-analog converter (DAC). This ADC runs at 500kSPS and converts the analog channel inputs, CH0 to CH15.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Single-Ended Analog Input In applications where the signal source has high impedance, it is recommended to buffer the analog input before applying it to the ADC. The analog input range can be programmed to be either 0V to VREF or 0V to (2 · VREF). In 2 · VREF mode, the input is effectively divided by two before the conversion takes place. Note that the voltage with respect to GND on the ADC analog input pins cannot exceed AVDD.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com Conversion Mode Two types of ADC conversions are available: direct mode and auto mode. The CMODE (conversion mode) bit of the AMC Configuration 0 Register specifies the conversion mode. In direct mode, each analog channel within the specified group is converted a single time. After the last channel is converted, the ADC goes into an idle state and waits for a new trigger. Auto mode is a continuous operation.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 When any of following events occur, the current conversion cycle stops immediately: • A new trigger is issued. • The conversion mode changes. • Either ADC channel register is rewritten. • Any of the analog input threshold registers is rewritten. When a new external or internal trigger activates, the ADC starts a new conversion cycle. The internal trigger should not be issued at the same time the conversion mode is changed.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com ADC Data Format For a single ended input, the conversion result is stored in straight binary format. For a differential input, the results are stored in twos complement format. SCLK Clock Noise Reduction To avoid noise caused by the bus clock, it is recommended that no bus clock activity occurs for at least the conversion process time immediately after the ADC conversion starts.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Handshaking with the Host (see AMC Configuration Register 0) The DAV pin and the DAVF (data available flag) bit in AMC Configuration Register 0 provide handshaking with the host. Pin and bit status depend on the conversion mode (direct or auto), as shown in Figure 84 and Figure 85.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com Data Available Pin (DAV) DAV is an output pin that indicates the completion of ADC conversions. The DAVF bit in AMC Configuration Register 0 determines the status of the DAV pin. In direct mode, after the selected group of input channels have been converted and the ADC has been stopped, the DAVF bit is set to '1' and the DAV pin is driven to logic low (active).
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 SECONDARY ADC/TEMPERATURE SENSOR OPERATION The AMC7812 contains one local and two remote temperature sensors. The temperature sensors continuously monitor the three temperature inputs, and new readings are automatically available every cycle. The on-chip integrated temperature sensor (shown in Figure 86) is used to measure the device temperature, and two remote diode sensor inputs are used to measure the two external temperatures.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com The AMC7812 has three temperature sensors: two remote (D1 and D2) and one on-chip (LT). If any sensor is not used, it can be disabled by clearing the corresponding enable bit (bits D2EN, D1EN, and LTEN of the Temp Configuration Register). When disabled, the sensors are not converted. The AMC7812 continuously monitors the selected temperature sensors in the background, leaving the user free to perform conversions on the other channels.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Remote Sensing Diode Errors in remote temperature sensor readings are typically the consequence of the ideality factor and current excitation used by the AMC7812 versus the manufacturer-specified operating current for a given transistor. Some manufacturers specify a low-level (ILOW) and high-level (IHIGH) current for the temperature-sensing substrate transistors. The AMC7812 uses 6μA for ILOW and 120μA for IHIGH.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com Filtering Figure 88 shows the connection of recommended (a) NPN or (b) PNP transistors. Remote junction temperature sensors are usually implemented in a noisy environment. Noise is most often created by fast digital signals, and it can corrupt measurements. The AMC7812 has a built-in 65kHz filter on the inputs of D+ and D-, to minimize the effects of noise.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 REFERENCE OPERATION The following sections describe the operation of the internal and external references. Internal Reference The AMC7812 includes a 2.5V internal reference. The internal reference is externally available at the REF-OUT pin. A 100pF to 10nF capacitor is recommended between the reference output and GND for noise filtering. The internal reference is a bipolar transistor-based, precision bandgap voltage reference.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com DAC OPERATION The AMC7812 contains 12 DACs that provide digital control with 12 bits of resolution using an internal or external reference. The DAC core is a 12-bit string DAC and output buffer. The DAC drives the output buffer to provide an output voltage. Refer to the DAC Configuration Register for details. Figure 91 shows a function block diagram of the DAC architecture.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 DAC Output The output range is programmable from 0 to (2 · VREF) or from 0 to (5 · VREF), depending on the gain bits in the DAC Gain Register. The maximum output is AVCC. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0V to AVCC. The source and sink capabilities of the output amplifier can be seen in the Typical Characteristics. The slew rate is 1.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com Synchronous Load, Asynchronous Load, and Output Updating The SLDA-n (synchronous load) bit of the DAC Configuration Register determines the DAC updating mode, as shown in Table 5. When SLDA-n is cleared to '0', asynchronous mode is active, the DAC Latch updates immediately after writing to the DAC-n-Data Register, and the output of DAC-n changes accordingly. Table 5.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Clear DACs DAC-n can be cleared using hardware or software as shown in Figure 93. When DAC-n goes to a clear state, it is immediately loaded with predefined code in the DAC-n-CLR-Setting Register, and the output is set to the corresponding level to shut down the external LDMOS device. However, the DAC-DATA-n Register does not change.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com Alarm Operation The AMC7812 continuously monitors all analog inputs and temperatures in normal operation. When any input is out of the specified range, an alarm triggers. When an alarm state occurs, the corresponding individual alarm bit in the Status Register is set ('1'). Global alarm bit GALR in AMC Configuration Register 0 is the OR of individual alarms, see Figure 94.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Analog Input Out-of-Range Alarm The AMC7812 provides out-of-range detection for four individual analog inputs (CH0, CH1, CH2, and CH3) as shown in Figure 95. When the measurement is out-of-range, the corresponding alarm bit in the Status Register is set to '1' to flag the out-of-range condition.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com ALARM pin The ALARM pin is a global alarm indicator. ALARM is an open-drain pin, as Figure 97 illustrates; an external pull-up resistor is required. When the pin is activated, it goes low. When the pin is inactive, it is in Hi-Z status. The ALARM pin works as an interrupt to the host so that it may query the Status Register to determine the alarm source.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Hysteresis The AMC7812 continuously monitors the analog input channels and temperatures. If any of the alarms are out of range and the alarm is enabled, its alarm bit is set ('1'). However, the alarm condition is cleared only when the conversion result returns to a value of at least hys below the value of High Threshold Register, or hys above the value of Low Threshold Register.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com GENERAL-PURPOSE INPUT/OUTPUT PINS (GPIO-0 to GPIO-7) The AMC7812 has eight GPIO pins. The GPIO-0, -1, -2 and -3 pins are dedicated to general, bidirectional, digital I/O signals. GPIO-4, GPIO-5, GPIO-6 and GPIO-7 are dual-function pins and can be programmed as either bidirectional digital I/O pins or remote temperature sensors D1 and D2. When D1 or D2 is disabled, the pins work as a GPIO.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 POWER SUPPLY SEQUENCE The preferred (not required) order for applying power is IOVDD, DVDD/AVDD and then AVCC. All registers initialize to the default values after these supplies have been established. Communication with the AMC7812 will be valid after a 250µS maximum power-on reset delay. The default state of all analog blocks is off as determined by the power-down register (6Bh).
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com F/S-Mode Protocol • The master initiates the data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 2. All I2C-compatible devices must recognize a start condition. • The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 AMC7812 Communication Protocol for I2C The AMC7812 uses the following I2C protocols. Writing a Single Word of Data to a 16-Bit Register (Figure 100) 1. The master device asserts a start condition. 2. The master then sends the 7-bit AMC7812 slave address followed by a zero for the direction bit, indicating a write operation. 3. The AMC7812 asserts an acknowledge signal on SDA. 4. The master sends a register address. 5.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com Writing Multiple Words to Different Registers (Figure 101) A complete word must be written to a register (high byte and low byte) for proper operation. 1. The master device asserts a start condition. 2. The master then sends the 7-bit AMC7812 slave address followed by a zero for the direction bit, indicating a write operation. 3. The AMC7812 asserts an acknowledge signal on SDA. 4. The master sends the first register address. 5.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Reading a Single Word from Any Register (Figure 102) 1. The master device asserts a start condition. 2. The master then sends the 7-bit AMC7812 slave address followed by a zero for the direction bit, indicating a write operation. 3. The AMC7812 asserts an acknowledge signal on SDA. 4. The master sends a register address. 5. The AMC7812 asserts an acknowledge signal on SDA. 6. The master device asserts a restart condition. 7.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com Reading the Same Register Multiple Times (Figure 103 and Figure 104) 1. The master device asserts a start condition. 2. The master then sends the 7-bit AMC7812 slave address followed by a zero for the direction bit, indicating a write operation. 3. The AMC7812 asserts an acknowledge signal on SDA. 4. The master sends a register address. 5. The AMC7812 asserts an acknowledge signal on SDA. 6. The master device asserts a restart condition.
AMC7812 www.ti.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com Serial Peripheral Interface (SPI) The AMC7812 can be controlled over a versatile 3-wire serial interface that operates at clock rates of up to 50MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards. The SPI communication command consists of a read/write bit, seven register address bits, and 16 data bits (as shown in Table 9), for a total of 24 bits.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Standalone Operation SDO SDI SCLK CS In standalone mode, as shown in Figure 105, each AMC7812 has its own SPI bus. The serial clock can be continuous or gated. The first falling edge of CS starts the operation cycle. Exactly 24 falling clock edges must be applied before CS is brought high again.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com Daisy-Chain Operation For systems that contain several AMC7812s, the SDO pin can be used to daisy-chain multiple devices together. This daisy-chain feature is useful in reducing the number of serial interface lines. The first falling edge of CS starts the operation cycle. SCLK is continuously applied to the Input Shift Register when CS is low.
AMC7812 www.ti.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com REGISTERS REGISTER MAP The AMC7812 has several 16-bit registers that consist of a high byte (8 MSBs) and a low byte (8 LSBs). An 8-bit register pointer points to the proper register. The pointer does not change after the operation. Table 10 lists the registers for the AMC7812. Note that the default values are for SPI operation; see the register descriptions for I2C default values. Table 10.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 TEMPERATURE DATA REGISTERS (Read-Only) In twos complement format, 0.125°C/LSB. LT-Temperature-Data Register (Address = 00h, Default 0000h, 0°C) Store the local temperature sensor reading in twos complement data format.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com TEMPERATURE CONVERSION RATE REGISTER (Read/Write, Address = 0Bh) When using the SPI, the following bit configuration must be used; default = 0007h. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 0 0 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 0 0 0 0 0 0 0 R2 R1 R0 When using the I2C interface, the following bit configuration must be used; default = 07FFh.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 η-FACTOR CORRECTION REGISTER (Read/Write, Addresses = 21h and 22h) Only the low byte is used; the high byte is ignored. When using the SPI interface, the following bit configuration must be used; (Default = 0000h).
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com ADC-n-DATA REGISTERS (Read-Only, Addresses = 23h to 32h) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 Bits[11:0] 0 0 A11 A10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADC data. Four ADC data registers are available. The ADC-n-Data Registers (where n = 0 to 15) store the conversion results of the corresponding analog channel-n, as shown in Table 15.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 DAC-n-DATA REGISTERS (Read/Write, Addresses = 33h to 3Eh, Default 0000h) Each DAC has a DAC data register to store the data [DAC11:DAC0] that is loaded into the DAC Latches. MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 Bits[11:0] 0 0 D11 D10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAC data.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com AMC CONFIGURATION REGISTER 0 (Read/Write, Address = 4Ch, Default = 2000h) Table 16. AMC Configuration Register 0 BIT NAME DEFAULT R/W 15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 14 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 13 CMODE 1 R/W ADC Conversion Mode Bit.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 AMC CONFIGURATION REGISTER 1 (Read/Write, Address = 4Dh, Default = 0070h) Table 17. AMC Configuration Register 1 BIT NAME DEFAULT R/W 15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. DESCRIPTION 14 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 13 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com ALARM CONTROL REGISTER (Read/Write, Address = 4Eh, Default = 0000h) The Alarm Control Register determines whether the ALARM pin is accessed when a corresponding alarm event occurs. However, this register does not affect the status bit in the Status Register. Note that the thermal alarm is always enabled. When the THERM_ALR bit = '1', the ALARM pin goes low, if the pin is enabled. Table 21.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Table 21. Alarm Control Register (continued) BIT 3 NAME EALR-D2-FAIL DEFAULT 0 R/W DESCRIPTION R/W D2 fail alarm enable bit. If EALR-D2-FAIL = '1', the D2-Fail alarm is enabled. When D2 fails, the D2-FAIL-ALR bit is set ('1'), the ALARM pin goes low (if enabled). If EALR-D2-FAIL = '0', the D2-FAIL alarm is masked. When D2 fails, the ALARM pin does not go low, but the D2-FAIL-ALR bit is set. Alarm latch disable bit.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com Table 22. Status Register BIT NAME DEFAULT R/W 15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'. 14 CH0-ALR 0 R CH0-ALR = '1' when single-ended channel 0 or differential input pair (CH0+/CH1–) is out of the range defined by the corresponding threshold registers. CH0-ALR = '0' when the analog input is not out of the specified range.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 ADC CHANNEL REGISTER 0 (Read/Write, Address = 50h, Default = 0000h) MSB BIT 15 BIT 14 BIT 13 0 SE0 BIT 12 DF (CH0+/ CH1–) SE1 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 DF (CH2+/ CH3–) SE4 SE5 SE6 SE7 SE8 SE9 SE10 SE11 SE12 BIT 11 BIT 10 SE2 SE3 These bits specify the external analog auxiliary input channels (CH0 to CH12) to be converted.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com ADC CHANNEL REGISTER 1 (Read/Write, Address = 51h, Default = 0000h) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 SE13 SE14 SE15 0 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 0 0 0 0 0 0 0 0 0 0 0 These bits specify the external analog auxiliary input channels (CH13, CH14,and CH 15) to be converted.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Table 26. AUTO-DAC-CLR-SOURCE Register (continued) BIT 11 10 9 8 7 6 5 4 3 NAME CH3-ALR-CLR LT-Low-ALRCLR LT-High-ALRCLR D1-Low-ALRCLR D1-High-ALRCLR D2-Low-ALRCLR D2-High-ALRCLR D1-FAIL-CLR D2-FAIL-CLR DEFAULT 0 0 0 0 0 0 0 0 0 R/W DESCRIPTION R/W CH3 alarm clear bit.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com AUTO-DAC-CLR-EN REGISTER (Read/Write, Address = 54h, Default = 0000h) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 ACLR 11 Bits[14:3] ACLR 10 ACLR 9 ACLR 8 ACLR 7 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 ACLR 6 ACLR 5 ACLR 4 ACLR 3 ACLR 2 ACLR 1 ACLR 0 0 0 0 ACLRn: Auto clear DAC-n enable bit. If ACLRn = '1', DAC-n is forced into a clear state when the alarm occurs.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 HW-DAC-CLR-EN 1 REGISTER (Read/Write, Address = 57h, Default = 0000h) This register determines which DAC is in a clear state when the DAC-CLR-1 pin goes low.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com ANALOG INPUT CHANNEL THRESHOLD REGISTERS (Read/Write, Addresses = 5Ah to 61h) Four analog auxiliary inputs (CH0, CH1, CH2, and CH3) and three temperature sensors (LT, D1, and D2) implement an out-of-range alarm function. Threshold-High-n and Threshold-Low-n (where n = 0, 1, 2, 3) define the upper bound and lower bound of the nth analog input range, as shown in Table 27. This window determines whether the nth input is out-of-range.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 TEMPERATURE THRESHOLD REGISTERS LT-High-Threshold Register (Read/Write, Address = 62h, Default = 07FFh, +255.875°C) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 THRH 11 THRH 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0 THRH 9 THRH 8 THRH 7 THRH 6 THRH 5 THRH 4 THRH 3 THRH 2 THRH 1 THRH 0 Bits [15:12] = ‘0' when read back.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com HYSTERESIS REGISTERS The hysteresis registers define the hysteresis in the alarm detection of an individual alarm. Hysteresis Register 0 (Read/Write, Address = 68h, Default = 0810h, 8 LSB) This register contains the hysteresis values for CH0 and CH1.
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 POWER-DOWN REGISTER (Read/Write, Address = 6Bh, Default = 0000h) After power-on or reset, all bits in the Power-Down Register are cleared to '0', and all the components controlled by this register are either powered-down or off. The Power-Down Register allows the host to manage the AMC7812 power dissipation.
AMC7812 SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (October 2012) to Revision E • Page Changed 2nd, 4th, 5th, and 7th values in Slave Address column in Table 8 .....................................................................
AMC7812 www.ti.com SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013 Changes from Revision A (March 2011) to Revision B Page • Added text to Desciption section .......................................................................................................................................... 1 • Added Reset Delay parameter to Electrical Characteristics .................................................................................................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 6-Sep-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant AMC7812SPAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 AMC7812SRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 AMC7812SRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AMC7812SPAPR HTQFP PAP 64 1000 367.0 367.0 55.0 AMC7812SRGCR VQFN RGC 64 2000 367.0 367.0 38.0 AMC7812SRGCT VQFN RGC 64 250 210.0 185.0 35.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
