Datasheet

tors are used. The time to change CR varies due to the
user-selectable count rates.
The overload flag (OVLD) is asserted when a discharge
overload is detected. PROG4 defines the overload
threshold, as defined in Table 4. OVLD remains as-
serted as long as the condition is valid.
The OVLD location is:
FLGS2 Bits
76543 2 1 0
- - - - - - - OVLD
Where OVLD is:
0IfV
SRO
>V
OVLD
1IfV
SRO
<V
OVLD
Program Pin Pull-Down Register (PPD)
The PPD register (address=07h) contains some of the pro-
gramming pin information for the bq2013H. The program
pins have a corresponding PPD bit location, PPD
1–6
.A
given location is set if a pull-down resistor has been de-
tected on its corresponding segment driver. For example, if
PROG
1
and PROG
4
have pull-down resistors, the con-
tents of PPD are xx001001.
PPD/PPU Bits
7 6 5 43210
RSVD RSVD PPU
6
PPU
5
PPU
4
PPU
3
PPU
2
PPU
1
RSVD RSVD PPD
6
PPD
5
PPD
4
PPD
3
PPD
2
PPD
1
Program Pin Pull-Up Register (PPU)
The PPU register (address=08h) contains the rest of the
programming pin information for the bq2013H. The pro-
gram pins have a corresponding PPU bit location, PPU
1–6
.
A given location is set if a pull-up resistor has been de-
tected on its corresponding segment driver. For example, if
PROG
3
and PROG
5
have pull-up resistors, the contents of
PPU are xx010100.
Output Control Register (OCTL)
The write-only OCTL register (address=0ah) provides the
system with a means to check the display connections for
the bq2013H. The segment drivers may be overwritten by
data from OCTL when bit 1 of OCTL, OCE, is set. The
data in bits OC
5–1
of the OCTL register (see Table 9 for de
-
tails) is output onto the segment pins, SEG
5–1
, respectively
if OCE=1. Whenever OCE is written to 1, the MSB of
OCTL should be set to a 1. The OCE register location
must be cleared to return the bq2013H to normal opera
-
tion. OCE may be cleared by either writing the bit to a
logic zero via the serial port or by resetting the bq2013H.
Offset Adjustment Register
The value in this register (address = 0bh) is used to cor-
rect NAC for the offset of the VFC. This register is ini-
tialized from the state of PROG
6
. The following are the
initial values:
■
0 = no offset correction
■
46 = -75µV correction
■
23 = -150µV correcton
The value is set by the equation:
Offset =
1
289∗V
COS
where V
COS
is the desired offset correction in volts.
Self-Discharge Rate Compensation
This register contains the value used to correct for the
self-discharge compensation. This value is initialized
from the state of PROG
3
. The following are the initial
values:
■ 235 = 1.6% per day
1
64






■
214 = 0.8% per day
1
128






■
88 = 0.2% per day
1
512






The value is set by the equation:
SDR 256
0.3296
C
SD
=−






where C
SD
is the self-discharge rate per day.
Digital Magnitude Filter (DMF)
The read-write DMF register (address=0dh) provides
the system with a means to change the default settings
of the digital magnitude filter. By writing different val-
ues into this register, the limits of V
SRD
and V
SRQ
can be
adjusted. The default value for the DMF is 250µV. The
value is set by the equation:
DMF
45
V
SRD, Q
=
where V
SRD,Q
is the desired filter threshold in mV.
Note: Care should be taken when writing to this regis
-
ter. A V
SRD
and V
SRQ
below the specified V
OS
may ad
-
versely affect the accuracy of the bq2013H.
14
bq2013H