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Features

➤

Multifunction charge/discharge

counter

➤

Resolves signals less than 12.5µV

➤

Internal offset calibration im

proves accuracy

➤

1024 bits of NVRAM configured as

128x8

➤

Internal temperature sensor for

self-discharge estimation

➤

Single-wire serial interface

➤

Dual operating modes:

Operating: <80µA

Sleep: <10µA

➤ REG output for low-cost mi-

croregulation

➤ Internal timebase eliminates ex-

ternal components

➤ 8-pin TSSOP or SOIC allows bat-

tery pack integration

General Description

The bq2018 is a low-cost charge/dis

charge counter peripheral packaged in

an 8-pin TSSOP or SOIC. It works

with an intelligent host controller, pro

viding state-of-charge information for

rechargeable batteries.

The bq2018 measures the voltage

drop across a low-value series sense

resistor between the negative termi

nal of the battery and the battery

pack ground contact. By using the ac

cumulated counts in the charge,

discharge, and self-discharge regis

ters, an intelligent host controller can

determine battery state-of-charge in

formation. To improve accuracy, an

offset count register is available. The

system host controller is responsible

for the register maintenance by reset-

ting the charge in/out and self-

discharge registers as needed.

The bq2018 also features 128 bytes

of NVRAM registers. The upper 13

bytes of NVRAM contain the capac

ity monitoring and status informa

tion. The RBI input operates from

an external power storage source

such as a capacitor or a series cell in

the battery pack, providing register

nonvolatility for periods when the

battery is shorted to ground or when

the battery charge state is not suffi

cient to operate the bq2018. During

this mode, the register backup cur

rent is less than 100nA.

Packaged in an 8-pin TSSOP or

SOIC, the bq2018 is small enough

to fit in the crevice between two A-

size cells or within the width of a

prismatic cell.

REG Regulator output

Supply voltage input

Ground

HDQ Data input/output

PN-201801.eps

8-Pin TSSOP or Narrow SOIC

REG

HDQ

WAKE

SR1

SR2

RBI

WAKE Wake-up output

SR1 Current sense input 1

SR2 Current sense input 2

RBI Register backup input

Pin Connections Pin Names

bq2018

Power Minder™ IC

SLUS003–JUNE 1999 C

Summary of content (25 pages)

PAGE 1
bq2018 Power Minder™ IC Features General Description ➤ Multifunction charge/discharge counter The bq2018 is a low-cost charge/discharge counter peripheral packaged in an 8-pin TSSOP or SOIC. It works with an intelligent host controller, providing state-of-charge information for rechargeable batteries. ➤ Resolves signals less than 12.
PAGE 2
bq2018 Pin Descriptions REG Functional Description General Operation Regulator output REG is the output of the operational transconductance amplifier (OTA) that drives an external pass n-channel JFET to provide an optional regulated supply. The supply is regulated at 3.7V nominal. VCC A host can use the bq2018 internal counters and timers to measure battery state-of-charge, estimate selfdischarge, and calculate the average charge and discharge current into and out of a rechargeable battery.
PAGE 3
bq2018 System I/O and Control WAKE Differential Dynamically Balanced VFC SR1 SR2 Bandgap Voltage Reference RAM and Counters 128 x 8 Calibration and Power Control TemperatureCompensated Precision Oscillator HDQ Timer RBI Counter Control Temperature Sensor d s VCC VDD (Internal) g Optional (External) REG Vref VSS BD201801.eps Figure 1. bq2018 Block Diagram Table 1.
PAGE 4
bq2018 BAT+ R6 d WAKE Q1 1K SST113 s C5 2 D2 BZX84C5V6 U1 0.01µF 1 2 3 4 VCC REG VCC VSS HDQ VCC WAKE SR1 SR2 RBI R2 8 7 6 5 BATC2 100K BQ2018 R1 0.1µF C1 R3 0.1µF 0.05 1W PACK100K C3 R5 HDQ 0.1µF 100 D3 2 D1 R4 BZX84C5V6 RBI C4 BAV99 1M 0.1µF 2018typAp.eps Figure 2. Typical Application counts by sensing the voltage difference across a lowvalue resistor between the negative terminal of the battery pack and the negative terminal of the battery.
PAGE 5
bq2018 7f 7f Discharge count high byte 7e Discharge count low byte 7d Charge count high byte 7c Charge count low byte 7b Self-discharge high byte 7a Self-discharge low byte 73 72 79 Discharge time high byte 78 Discharge time low byte User RAM 77 Charge time high byte 76 Charge time low byte 75 Mode/wake output enable 74 Temperature/clear 73 Offset register 00 FG201801.eps Figure 3.
PAGE 6
bq2018 Table 3. WOE Thresholds Table 4. Temperature Steps WOE3–1 (hex) VWOE (mV) 0h n/a 1h 3.840 2h 1.920 10–20° 2h × 1/2 3h 1.280 20–30° 3h 1 count/hr. 4h 0.960 30–40° 4h ×2 5h 0.768 40–50° 5h ×4 6h 0.640 50–60° 6h ×8 7h* 0.549 >60° 7h × 16 Temp Value (hex) SDR Count Rate <0° 0h × 1/8 0–10° 1h × 1/4 * Default value after POR.
PAGE 7
bq2018 Table 5. bq2018 Command and Status Registers Symbol CMDR DCRH DCRL CCRH CCRL SCRH SCRL DTCH DTCL CTCH CTCL MODE/ WOE TMP/CLR OFR RAM Notes: Register Name Loc.
PAGE 8
bq2018 low-power mode until HDQ goes high, indicating an external system is ready to access the bq2018. If HDQ transitions high prior to completion of the VOS calculation or if |VSR| > VWOE, then the calibration cycle is reset. The bq2018 then postpones the calibration cycle until the conditions are met. The calibration bit does not reset to zero until a valid calibration cycle is completed. The requirement for HDQ to remain low for the calibration cycle can be disabled by setting the OVRDQ bit to 1.
PAGE 9
bq2018 DTCH and DTCL increment at a rate of 16 counts per hour. Note: If a second rollover occurs, STC is cleared. Access to the bq2018 should be timed to clear CTCH/CTCL more often than every 170 days. The TMP/CLR register is used to force the reset of both the CTCH and CTCL to zero. of the discharge, and are incremented whenever VSR1 < VSR2. These registers continue to count beyond ffffh, so proper register maintenance should be done by the host system.
PAGE 10
bq2018 The slow time charge (STC) and slow time discharge (STD) flags indicate if the CTC or DTC registers have rolled over beyond ffffh. STC set to 1 indicates a CTC rollover; STD set to 1 indicates a DTC rollover. Temperature and Clear Register The TMP/CLR register (address = 74h) is used to give the present temperature step between < 0°C to > 60°C and clear the various count registers. The values of the TMP0–TMP2 (bits 5–7) denote the current temperature step sense by the bq2018 as outlined in Table 4.
PAGE 11
bq2018 The Clear bit locations are Offset Register (OFR) The OFR register (address = 73h) is used to store the calculated VOS of the bq2018. The OFR value can be used to cancel the voltage offset between VSR1 and VSR2. The up/down offset counter is centered at zero. The actual offset is an 8-bit two’s complement value located in OFR.
PAGE 12
bq2018 Absolute Maximum Ratings Symbol Parameter Minimum Maximum Uni t VCC Relative to VSS -0.3 +6.0 V HDQ Relative to VSS -0.3 +6.0 V VSS -0.3V VCC +3.0V V 1.0 mA All other pins IREG REG to VSS VSR1 / VSR2 Relative to VSS -0.3 +6.0 V TOPR Operating temperature - 20 +70 °C Note: Notes A 100kΩ series resistor is recommended to protect SR1 / SR2 in case of a shorted battery. Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
PAGE 13
bq2018 Performance Characteristics (TA = TOPR) Symbol Parameter Typical Maximum Unit Notes VOS Offset voltage ±500 µV Voltage offset between SR1 and SR2 OSC Timer accuracy 1.5 ±3.0 % VCC =3.5 - 3.9V (TA = 0–70°C) INR Integrated nonrepeatability error 0.5 1.0 % Measured repeatability given similar operating conditions INL Integrated non-linearity 1.0 2.0 % Add 0.05% per °C above or below 25°C and 0.5% per volt above or below 3.7V.
PAGE 14
bq2018 Break Timing tBR tB Host to bq2018 Write "1" Write "0" tSTRH tDSU tDH tSSU tCYCH bq2018 to Host Read "1" Read "0" tSTRB tDSUB tDV tSSUB tCYCB 14
PAGE 15
bq2018 8-Pin SOIC Narrow ~ SN Package Suffix Millimeters Inches Dimension A Min. Max. Min. Max. 1.52 1.78 0.060 0.070 A1 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.18 0.25 0.007 0.010 D 4.70 5.08 0.185 0.200 E 3.81 4.06 0.150 0.160 e 1.14 1.40 0.045 0.055 H 5.72 6.22 0.225 0.245 L 0.38 0.89 0.015 0.
PAGE 16
bq2018 8-Pin TSSOP ~ TS Package Suffix Millimeters Inches Dimension A Min. Max. Min. Max. - 1.10 - 0.043 A1 0.05 0.15 0.002 0.006 B 0.18 0.30 0.007 0.012 C 0.09 0.18 0.004 0.007 D 2.90 3.10 0.115 0.122 E 4.30 4.48 0.169 0.176 e 0.65BSC 0.0256BSC H 6.25 6.50 0.246 0.256 L 0.50 0.70 0.020 0.028 Notes: 1. Controlling dimension: millimeters. Inches shown for reference only. 2 'D' and 'E' do not include mold flash or protrusions.
PAGE 17
bq2018 Data Sheet Revision History Change No. Page No. 1 All 2 12 Note: Description Nature of Change Clarification of absolute maximum pin ratings Change 1 = Jan. 1999 B changes to Final from Dec. 1998 Preliminary data sheet. Change 2 = June 1999 C changes from Jan. 1999 B.
PAGE 18
bq2018 Ordering Information bq2018 Temperature Range: blank = Commercial (-20 to +70°C) Package Option: SN = 8-pin narrow SOIC TS = 8 pin TSSOP Device: bq2018 Power Minder IC 18
PAGE 19
Notes 19
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
PAGE 21
PACKAGE OPTION ADDENDUM www.ti.
PAGE 22
PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ2018SN-E1TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 BQ2018TS-E1TR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.
PAGE 24
PACKAGE MATERIALS INFORMATION www.ti.com 11-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ2018SN-E1TR SOIC D 8 2500 367.0 367.0 35.0 BQ2018TS-E1TR TSSOP PW 8 2000 367.0 367.0 35.
PAGE 25
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.