Datasheet

LED Display
SMB 1.1
JEITA and
Enhanced
Charging
Algorithm
Data Flash
Memory
SHA-1
Authentication
Fuse Blow
Detection & Logic
System Control
Over
Temperature
Protection
Temperature
Measurement
Oscillator
Over & Under
Voltage
Protection
Over Current
Protection
PreCharge FET
& GPOD Drive
Impedance
Track™ Gas
Gauging
Voltage
Measurement
Coulomb
Counter
N Channel FET
Drive
AFE HW Control
HW Over
Current & Short
Circuit Protection
Power Mode
Control
Watchdog
Cell Balancing
Cell Voltage
Multiplexer
Regulators
SMBD
SMBC
DISP
LED1
LED2
LED3
LED4
LED5
PFIN
SAFE
PMS
ZVCHG
GPOD DSG
CHG
PACK
VCC
BAT
VSS
RBI
MSRT
RESET
ALERT
VCELL+
VC1
VC2
VC3
VC4
VC5
REG33
REG25
ASRN
ASRP
GSRN
GSRP
TS2
TS1
TOUT
VC1
VC4
VDD
VC2
CD
GND
OUT
VC3
+
+
+
+
PACK+
PACK–
RSNS
5 m
Ω
– 20 m
Ω
typ
bq294xx
PRES
bq20z655
SLUSAH8A –APRIL 2011–REVISED MAY 2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE THERMAL DATA
THERMAL INFORMATION
bq20z655
THERMAL METRIC
(1)
TSSOP UNITS
44 PINS
θ
JA, High K
Junction-to-ambient thermal resistance
(2)
60.9
θ
JC(top)
Junction-to-case(top) thermal resistance
(3)
15.3
θ
JB
Junction-to-board thermal resistance
(4)
30.2
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.3
ψ
JB
Junction-to-board characterization parameter
(6)
27.2
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance
(7)
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
SYSTEM PARTITIONING DIAGRAM
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