Datasheet

bq20z655
www.ti.com SLUSAH8A –APRIL 2011–REVISED MAY 2012
TERMINAL FUNCTIONS
TERMINAL
I/O
(1)
DESCRIPTION
NO. NAME
1 DSG O High side N-chan discharge FET gate drive
Battery pack input voltage sense input. It also serves as device wake up when device is in shutdown
2 PACK IA, P
mode.
Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to
3 VCC P
ensure device supply either from battery stack or battery pack input.
4 ZVCHG O P-chan pre-charge FET gate drive
High voltage general purpose open drain output. It can be configured to be used in pre-charge
5 GPOD OD
condition.
Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET
6 PMS I connected at CHG pin. Connect to VSS to disable 0-V pre-charge using charge FET connected at
CHG pin.
7 VSS P Negative supply voltage input. Connect all VSS pins together for operation of device.
8 REG33 P 3.3-V regulator output. Connect at least a 2.2-μF capacitor to REG33 and VSS.
9 TOUT P Thermistor bias supply output
Internal cell voltage multiplexer and amplifier output. Connect a 0.1-μF capacitor to VCELL+ and
10 VCELL+ —
VSS.
Alert output. In case of short circuit condition, overload condition, and watchdog time out, this pin will
11 ALERT OD
be triggered.
12 COM/TP — Output/open drain: LCD common connection
13 TS1 IA 1
st
Thermistor voltage input connection to monitor temperature
14 TS2 IA 2
nd
Thermistor voltage input connection to monitor temperature
15 PRES I Active low input to sense system insertion. Typically requires additional ESD protection.
Active low input to detect secondary protector status, and to allow the bq20z655 to report the status
16 PFIN I
of the 2
nd
level protection input
17 SAFE OD Active high output to enforce additional level of safety protection; e.g., fuse blow
SMBus data open-drain bidirectional pin used to transfer address and data to and from the
18 SMBD I/OD
bq20z655
A logical high on this pin only affects the normal operation on the charge FET when the battery is in
19 CE —
charge/relax mode. For a logic low, the normal bq20z655 firmware controls the charge FET.
20 SMBC I/OD SMBus clock open-drain bidirectional pin used to clock the data transfer to and from the bq20z655
21 DISP I Input: In LED mode, this is the display enable input.
22 VSS P Negative supply voltage input. Connect all VSS pins together for operation of device.
23 LED1/SEG1 I Output/open drain: LED 1 current sink. LCD segment 1
24 LED2/SEG2 I Output/open drain: LED 2 current sink. LCD segment 2
25 LED3/SEG3 I Output/open drain: LED 3 current sink. LCD segment 3
26 LED4/SEG4 I Output/open drain: LED 4 current sink. LCD segment 4
27 LED5/SEG5 I Output/open drain: LED 5 current sink. LCD segment 5
28 GSRP IA Coulomb counter differential input. Connect to one side of the sense resistor.
29 GSRN IA Coulomb counter differential input. Connect to one side of the sense resistor.
Master reset input that forces the device into reset when held low. Must be held high for normal
30 MRST I
operation. Connect to RESET for correct operation of device.
31 VSS P Negative supply voltage input. Connect all VSS pins together for operation of device.
32 REG25 P 2.5-V regulator output. Connect at least a 1-mF capacitor to REG25 and VSS.
RAM / Register backup input. Connect a capacitor to this pin and VSS to protect loss of
33 RBI P
RAM/Register data in case of short circuit condition.
34 VSS P Negative supply voltage input. Connect all VSS pins together for operation of device.
35 RESET O Reset output. Connect to MSRT.
36 ASRN IA Short circuit and overload detection differential input. Connect to sense resistor.
37 ASRP IA Short circuit and overload detection differential input. Connect to sense resistor.
(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
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