Datasheet

q
JA
+
T
J
* T
A
P
P +
ƪǒ
V
IN
* V
OUT
Ǔ ǒ
I
OUT
) I
BAT
Ǔƫ
)
ƪǒ
V
OUT
* V
BAT
Ǔ ǒ
I
BAT
Ǔƫ
bq24030, bq24031
bq24032A, bq24035, bq24038
www.ti.com ............................................................................................................................................... SLUS618H –AUGUST 2004–REVISED OCTOBER 2009
APPLICATION INFORMATION
Selecting the Input and Output Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor on each input (AC and USB). A
0.1-μF ceramic capacitor, placed in close proximity to AC and USB to VSS pins, works well. In some applications
depending on the power supply characteristics and cable length, it may be necessary to add an additional 10-μF
ceramic capacitor to each input.
The bqTINY III-series only requires a small output capacitor for loop stability. A 0.1-μF ceramic capacitor placed
between the OUT and VSS pin is typically sufficient.
The integrated LDO requires a maximum of 1-μF ceramic capacitor on its output. The output does not require a
capacitor for a steady-state load but a 0.1-μF minimum capacitance is recommended.
It is recommended to install a minimum of 33-μF capacitor between the BAT pin and VSS (in parallel with the
battery). This ensures proper hot plug power up with a no-load condition (no system load or battery attached).
Thermal Considerations
The bqTINY III-series is packaged in a thermally enhanced MLP package. The package includes a QFN thermal
pad to provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB
design guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment
(SLUA271). The power pad should be tied to the VSS plane. The most common measure of package thermal
performance is thermal impedance (θ
JA
) measured (or modeled) from the chip junction to the air surrounding the
package surface (ambient).
The mathematical expression for θ
JA
is:
(10)
where
T
J
= chip junction temperature
T
A
= ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of θ
JA
include:
• whether or not the device is board mounted
• trace size, composition, thickness, and geometry
• orientation of the device (horizontal or vertical)
• volume of the ambient air surrounding the device under test and airflow
• whether other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power
FET. It can be calculated from Equation 11:
(11)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See Figure 1. Typically the Li-ion battery's voltage
quickly (< 2 V minutes) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery
above V
(LOWV)
). Therefore, it is customary to perform the steady-state thermal design using 3.5 V as the
minimum battery voltage because the system board and charging device does not have time to reach a
maximum temperature due to the thermal mass of the assembly during the early stages of fast charge. This
theory is easily verified by performing a charge cycle on a discharged battery while monitoring the battery voltage
and chargers power pad temperature.
Copyright © 2004–2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): bq24030, bq24031 bq24032A, bq24035, bq24038