Datasheet

Drive
Logic
V
CC
To
ISET2
R1
R2
ToISET2
V
CC
Q1
Q2
Drive
Logic
R1/R2Divider
setto0.9V
Whichisthe
FloatVoltage
OR
bq24050
bq24052
bq24055
www.ti.com SLUS940B –SEPTEMBER 2009–REVISED JUNE 2012
ISET2
Is a 3-state input and programs the Input Current Limit/Regulation Threshold. A low will program a regulated fast
charge current via the ISET resistor and is the maximum allowed input/output current for any ISET2 setting, Float
will program a 100mA Current limit and High will program a 500mA Current limit. Note that initially the D+/D–
detection will latch the charge mode according to the source detected (dedicated charger: ISET; USB Host: at
100mA) until the ISET2 pin has changed states, indicating the processor or transceiver is controlling the pin.
The detection routine registers the input level (Low–High-Z–High) of the ISET2 pin ~532 μs after applying input
power (V
IN
> 3.4 V – UVLO). After the detection routine is complete, which is ~100 ms after a pull-up on the D+
or D– line or after ~570 ms if no pull-up, the IC monitors the ISET2 pin for a change of state. If the state changes
(Low–High-Z–High) from the one registered, for more than 5 μs, then the "detected" latched charge mode is
released and is then controlled by the ISET2 pin. The completion of the detection routine varies due to the
mechanical-plugging action of the USB cable; therefore, it is best to wait ≥ 600 ms after V
IN
> 3.4 V to take
control of the ISET2 pin.
The following illustration shows two configurations for driving the 3-state ISET2 pin:
Copyright © 2009–2012, Texas Instruments Incorporated 23