Datasheet

bq24195
bq24195L
SLUSB97 –OCTOBER 2012 www.ti.com
I
2
C Registers
Address: 6BH. REG00-07 support Read and Write. REG08-0A are read only.
Input Source Control Register REG00 (default 00110000, or 30)
BIT DESCRIPTION
Bit 7 EN_HIZ 0 – Disable, 1 – Enable Default: Disable (0)
Input Voltage Limit
Bit 6 VINDPM[3] 640mV Offset 3.88V, Range: 3.88V-5.08V
Default: 4.36V (0110)
Bit 5 VINDPM[2] 320mV
Bit 4 VINDPM[1] 160mV
Bit 3 VINDPM[0] 80mV
Input Current Limit (Actual input current limit is the lower of I
2
C and ILIM)
Bit 2 IINLIM[2] 000 – 100mA, 001 – 150mA, 010 – 500mA, Default SDP: 100mA (000)(OTG pin=0) or 500mA (010)
011 – 900mA, 100 – 1.2A, 101 – 1.5A, (OTG pin=1)
Bit 1 IINLIM[1]
110 – 2A, 111 – 3A Default DCP/CDP: 1.5A (101)
Bit 0 IINLIM[0]
Power-On Configuration Register REG01 (default 00011011, or 1B)
BIT DESCRIPTION NOTE
Bit 7 Register Reset 0 – Keep current register setting, Default: Keep current register setting (0)
Back to 0 after register reset
1 – Reset to default
Bit 6 I
2
C Watchdog 0 – Normal ; 1 – Reset Default: Normal (0)
Timer Reset Back to 0 after timer reset
Charger Configuration
Bit 5 CHG_CONFIG[1] 00 – Charge Disable, 01 – Charge Battery, Default: Charge Battery (01)
10/11 – OTG
Bit 4 CHG_CONFIG[0]
Minimum System Voltage Limit
Bit 3 SYS_MIN[2] 0.4V Offset: 3.0V, Range 3.0V-3.7V
Default: 3.5V (101)
Bit 2 SYS_MIN[1] 0.2V
Bit 1 SYS_MIN[0] 0.1V
Bit 0 Reserved 1 - Reserved
Charge Current Control Register REG02 (default 01100000, or 60)
BIT DESCRIPTION NOTE
Fast Charge Current Limit
Bit 7 ICHG[5] 2048mA Offset: 512mA
Range: 512-4544mA (bq24195)
Bit 6 ICHG[4] 1024mA
Range: 512-2496mA (bq24195L)
Bit 5 ICHG[3] 512mA
Default: 2048mA (011000)
Bit 4 ICHG[2] 256mA
Bit 3 ICHG[1] 128mA
Bit 2 ICHG[0] 64mA
Bit 1 Reserved 0 - Reserved
Bit 0 FORCE_20PCT 0 – ICHG as REG02[7:2] programmed Default: ICHG as REG02[7:2] programmed (0)
1 – ICHG as 20% of REG02[7:2] programmed
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