Datasheet

bq24270
bq24271
SLUSB10 –JUNE 2012 www.ti.com
overall charging efficiency for long. If the die temperature does heat up, the thermal regulation circuit reduces the
charge current to maintain a die temperature less than 125°C. If the current limit for the SYS output is reached
(limited by the input current limit, or V
(IN_DPM)
), the SYS output drops to the V
(MINSYS)
output voltage. When this
happens, the current is reduced to provide the system with all the current that is needed while maintaining the
minimum system voltage. If the charge current is reduced to 0 mA, pulling further current from SYS causes the
output to fall to the battery voltage and enter supplement mode (see the Dynamic Power Path Management
section for more details
Once the battery is charged enough to where the system voltage begins to rise above V
SYS(REG)
(approximately
3.5 V), the battery FET is turned on fully and the battery is charged with the full programmed charge current set
by the I
2
C interface, I
(CHARGE)
. The slew rate for fast charge current is controlled to minimize the current and
voltage over-shoot during transient. The charge current is regulated to I
(CHARGE)
until the battery is charged to the
regulation voltage. Once the battery voltage is close to the regulation voltage, V
(BATREG)
, the charge current is
tapered down as shown in Figure 3 while the SYS output remains connected to the battery. The voltage
regulation feedback occurs by monitoring the battery-pack voltage between the BAT and PGND pins. The
V
(BATREG)
is targeted for single-cell voltage batteries and has an adjustable regulation voltage (3.5 V to 4.44 V)
programmed using the I
2
C interface
The devices monitor the charging current during the voltage regulation phase. Once the termination threshold,
I
(TERM)
, is detected and the battery voltage is above the recharge threshold, the devices terminate charge and
turn off the battery charging FET and enters battery detection. If a battery is detection (See the Battery Detection
section), the devices enter charge done. The system output is regulated to the V
SYS(REG)
and supports the full
current available from the input and the battery supplement mode is available (see the Dynamic Power Path
Management section for more details). The termination current level is programmable. To disable the charge
current termination, the host sets the charge termination bit (TE) of charge control register to 0, see the to I
2
C
section for details.
1. The battery voltage falls below the V
(BATREG)
- V
(RCH)
threshold.
2. V
(USB)
toggle
3. CE bit toggle or RESET bit is set
4. Hi-Z bit toggle
Battery Detection
When termination conditions are met, a battery detection cycle is started. During battery detection, I
(DETECT)
is
pulled from V
(BAT)
for t
(DETECT)
to verify there is a battery. If the battery voltage remains above V
(DETECT)
for the full
duration of t
(DETECT)
, a battery is determined to present and the IC enters “Charge Done”. If V
(BAT)
falls below
V
(DETECT)
, a “Battery Not Present” fault is signaled and battery detection continues. The next cycle of battery
detection, the bq24270 and bq24271 turn on I
(BATSHRT)
for t
(DETECT)
. If V
(BAT)
rises to V
(DETECT)
, the current source
is turned off and after t
(DETECT)
, the battery detection continues through another current sink cycle. Battery
detection continues until charge is disabled or a battery is detected. Once a battery is detected, the fault status
clears and a new charge cycle begins. Battery detection is not run when termination is disabled.
Dynamic Power Path Management
The bq24270 and bq24271 feature a SYS output that powers the external system load connected to the battery.
This output is active whenever a source is connected to USB or BAT. The following sections discuss the
behavior of SYS with a source connected to the supply or a battery source only.
Input Source Connected
When a valid input source is connected, the buck converter turns on to power the load on SYS. The STAT/INT
show an interrupt with 128 µs pulse to tell the host that something has changed. The FAULT bits read normal,
and the Supply Status register shows that a new supply is connected. The CE bit (bit 1) in the control register
(0x02) determines whether a charge cycle is initiated. By default, the bq24270 and bq24271 (CE = 0) enable a
charge cycle when a valid input source is connected. When the CE bit is 1 and a valid input source is connected,
the battery FET is turned off and the SYS output is regulated to the V
SYS(REG)
programmed by the V
(BATREG)
threshold in the I
2
C register. A charge cycle is initiated when the CE bit is written to a 0.
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