Datasheet

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bq24270

bq24271

SLUSB10 –JUNE 2012

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D+ and D- Based Adapter Detection for the USB Input (D+ and D-, bq24270)

The bq24270 contains a D+ and D– based adapter detection circuit that is used to program the input current limit

for the USB input during DEFAULT mode. D+ and D– detection is only performed in DEFAULT mode unless

forced by the D+ and D– EN bit in host mode.

By default the USB input current limit is set to 100 mA. When USB is asserted the bq24270 performs a charger

source identification to determine if it is connected to an SDP (USB port) or CDP and DCP (dedicated charger).

When the detection is initiated, the first step is the connection detection as described in BC1.2. This step detects

when the D+ and D- lines are connected to the bq24270. Once this connection is made, the circuit moves to the

Primary Detection. If the connection detection has not completed within 500 ms, the D+ and D- detection selects

100 mA for the unknown input source. The primary detection complies with the method described in BC1.2.

During primary detection, the D+ and D- lines are tested to determine if the port is an SDP or CDP and DCP. If a

CDP and DCP is detected the input current limit is increased to 1.5 A, if an SDP is detected the current limit

remains at 100 mA, until changed via the I

C interface. Secondary detection is not performed.

Automatic detection is performed only if V

(D+)

and V

(D–)

are less than 0.6 V to avoid interfering with the USB

transceiver which may also perform D+ and D- detection when the system is running normally. However, D+ and

D– can be initiated at any time by the host by setting the D+ and D– EN bit in the Control/Battery Voltage

circuitry is disconnected from the D+ and D- pins to avoid interference with USB data transfer. When a command

is written to change the input current limit in the I

C, this overrides the current limit selected by D+/D- detection.

USB Input Current Limit Selector Input (PSEL, bq24271)

The bq24271 contains a PSEL input that is used to program the input current limit for USB during DEFAULT

mode. Drive PSEL high to indicate a USB source is connected to the USB input and program the 500 mA current

limit for USB. Drive PSEL low to indicate that an AC Adapter is connected to the )USB input. When PSEL is low,

the IC starts up with a 1.5 A current limit for USB. Once an I

C write is done, PSEL has no effect on the input

current limit until the watchdog timer expires.

Hardware Chip Disable Input (CD)

The bq24270 and bq24271 contain a CD input that is used to disable the IC and place the devices into high-

impedance mode. Drive CD low to enable charge and enter normal operation. Drive CD high to disable charge

and place the devices into high-impedance mode. Driving CD resets the safety timer.

LDO Output (DRV)

The bq24270 and bq24271 contain a linear regulator (DRV) that is used to supply the internal MOSFET drivers

and other circuitry. Additionally, DRV supplies up to 10mA external loads to power the STAT LED or the USB

transceiver circuitry. The maximum value of the DRV output is 5.45 V so it ideal for protecting voltage sensitive

USB circuits from high voltage fluctuations in the supply. The LDO is on whenever a supply is connected to the

USB input of the bq24270 and bq24271. The DRV is disabled under the following conditions:

1. V

(USB)

< UVLO

2. V

(USB)

< V

SLP

3. Thermal Shutdown

4. OTG_LOCK bit set to '1'

External NTC Monitoring (TS)

The I

C interface allows the user to implement the JEITA standard for systems where the battery pack thermistor

is monitored by the host. Additionally, the bq24270 and bq24271 provide a flexible, voltage based TS input for

monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a

safe temperature during charging. The devices enable the user to implement the JEITA. The JEITA specification

is shown in Figure 6.

Product Folder Link(s): bq24270 bq24271