Datasheet

DISABLE
V
DRV
TEMP
PACK+
PACK-
+
+
+
+
V
DRV
TS COLD
TS HOT
TS WARM
TS COOL
1 x Charge/
0.5 x Charge
V
BAT(REG)
– 140mV
TS
bq2427x
RHI
RLO
RLO × 0.383 × RHI
RWARM =
RLO - RLO × 0.383 - RHI × 0.383
RLO × 0.564 × RHI
RCOOL =
RLO - RLO × 0.564 - RHI × 0.564
bq24270
bq24271
SLUSB10 –JUNE 2012 www.ti.com
(3)
(4)
Figure 7. TS Circuit
If the TS function is not used, connect TS to DRV directly to disable the feature. Additionally, the TS function can
be disabled in the I
2
C by writing to the EN_TS bit. When the TS is disabled, the status registers always read
“Normal”.
Thermal Regulation and Protection
During the charging process, to prevent the IC from overheating, bq24270 and bq24271 monitor the junction
temperature, T
J
, of the die and begins to taper down the charge current once T
J
reaches the thermal regulation
threshold, T
REG
. The charge current is reduced to zero when the junction temperature increases about 10°C
above T
REG
. Once the charge current is reduced, the system current is reduced while the battery supplements
the load to supply the system. This may cause a thermal shutdown of the devices if the die temperature rises too
high. At any state, if T
J
exceeds T
SHTDWN
, the devices suspend charging and disables the buck converter. During
thermal shutdown mode, PWM is turned off, and the timers are suspended, and a single 128 μs pulse is sent on
the STAT and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I
2
C. A
new charging cycle begins when T
J
falls below T
SHTDWN
by approximately 10°C.
Input Voltage Protection in Charge Mode
Sleep Mode
The bq24270 and bq24271 enter the low-power sleep mode if the voltage on V
(USB)
falls below sleep-mode
entry threshold, V
(BAT)
+ V
(SLP)
, and V
(VBUS)
is higher than the undervoltage lockout threshold, V
UVLO
. This
feature prevents draining the battery during the absence of V
(USB)
. When V
(USB)
< V
(BAT)
+ V
(SLP)
, the devices
turn off the PWM converter, turn on the battery FET, drive BGATE to GND, send a single 128 μs pulse on
the STAT and INT outputs, and update the STATx and FAULT_x bits in the status registers. Once V
(USB)
>
V
(BAT)
+ V
(SLP)
, the STATx and FAULT_x bits are cleared and the devices initiate a new charge cycle.
20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): bq24270 bq24271