Datasheet

bq24270
bq24271
SLUSB10 –JUNE 2012 www.ti.com
Charge Status Outputs (STAT, INT)
The STAT output is used to indicate operation conditions for bq24270 and bq24271. STAT is pulled low during
charging when EN_STAT bit in the control register (0x02h) is set to “1”. When charge is complete or disabled,
STAT is high impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status
of STAT during different operation conditions is summarized in Table 1. STAT drives an LED for visual indication
or can be connected to the logic rail for host communication. The EN_STAT bit in the control register (00H) is
used to enable/disable the charge status for STAT. The interrupt pulses are unaffected by EN_STAT and will
always be shown. The INT output is identical to STAT and is used to interface with a low voltage host processor
Table 1. STAT Pin Summary
Charge State STAT and INT behavior
Charge in progress and EN_STAT=1 Low
Other normal conditions High-Impedance
Status Changes: Supply Status Change (plug in or
removal), safety timer fault, watchdog expiration,
128-µs pulse, then High Impedance
sleep mode, battery temperature fault (TS), battery
fault (OVP or absent), thermal shutdown
The bq24270 and bq24271 contain a good battery monitor circuit that places the devices into high-z mode if the
battery voltage is above the BATGD threshold while in DEFAULT mode. This function is used to enable
compliance to the battery charging standard that prevents charging from an un-enumerated USB host while the
battery is above the good battery threshold. If the devices are in HOST mode, it is assumed that USB host has
been enumerated and the good battery circuit has no effect on charging.
SERIAL INTERFACE DESCRIPTION
The bq24270 and bq24271 use an I
2
C compatible interface to program charge parameters. I
2
C is a 2-wire serial
interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1, January 2000). The bus
consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and
SCL lines are pulled high. All the I
2
C compatible devices connect to the I
2
C bus through open drain I/O pins,
SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device.
The devices work as a slave and support the following data transfer modes, as defined in the I
2
C Bus
Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the battery
charging solution, enabling most functions to be programmed to new values depending on the instantaneous
application requirements. Register contents remain intact as long as battery voltage remains above 2.5 V
(typical). The I
2
C circuitry is powered from V
(BUS)
when a supply is connected. If the V
(BUS)
supply is not
connected, the I
2
C circuitry is powered from the battery through BAT. The battery voltage must stay above 2.5 V
with no input connected in order to maintain proper operation
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The devices only support 7-bit addressing. The 7-bit address is defined as ‘1101011’
(6Bh).
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 9. All I
2
C - compatible devices should
recognize a start condition.
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