Datasheet
D
TI YMLLLLS
bq24270
bq24271
0-Pin A1 Marker, TI-TI Letters, YM-Year Month Date Code,
LLLL-Lot Trace Code, S-Assembly Site Code
USBUSBUSBAGND
PMIDPMIDPMIDBYP
SWSWSWSW
PGNDPGNDPGND
SW
SDA
PGND
BOOTCD
AGND
BYP
PGND
D- SCL
1 2 3 4 5
A
B
C
D
E
AGND
SW
D+
BYP
PGND
6
BGATE
DRVSYSSYS INT
F
SYS
AGND
SW
PGND
BYP
PGND
SYS
TS PGNDBATBAT STATBATBAT
G
7
bq24270
bq24271
www.ti.com
SLUSB10 –JUNE 2012
The following provides some guidelines:
• To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be
placed as close as possible to the bq24270 and bq24271
• Place 4.7 µF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1µF input capacitor GNDs as close to the respective PMID cap GND
and PGND pins as possible to minimize the ground difference between the input and PMID.
• The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the
IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the
PGND pin.
• Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-
coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
• The high-current charge paths into USB, BAT, SYS and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
• For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance as the board pulls heat away from the IC.
PACKAGE SUMMARY
CHIP SCALE PACKAGING DIMENSIONS
The devices are available in a 49-bump chip scale package (YFF, NanoFree™). The package dimensions are:
• D – 2.78mm ± 0.05mm
• E – 2.78mm ± 0.05mm
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): bq24270 bq24271