Datasheet

bq24270
bq24271
www.ti.com SLUSB10 –JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 3, V
(UVLO)
< V
(USB)
< V
(OVP)
AND V
(USB)
> V
(BAT)
+V
(SLP)
, T
J
= 0°C–125°C and T
J
= 25°C for typical values
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENT LIMITING
I
(USBLIM)
= USB100 90 95 100
I
(USBLIM)
= USB500 400 475 500
I
(USBLIM)
= USB150 135 142.5 150
Input current limit threshold (USB USB charge mode, V
(USB)
= 5 V, DC Current
I
(USBLIM)
mA
input) pulled from SW
I
(USBLIM)
= USB900 800 850 900
I
(USBLIM)
= USB800 700 750 800
I
(USBLIM)
= 1.5A 1250 1400 1500
V
(IN_DPM)
Input based DPM threshold range 4.2 4.76 V
Charge mode, programmable via I
2
C
V
(IN_DPM)
threshold Accuracy –2% 2%
VDRV BIAS REGULATOR
V
(DRV)
Internal bias regulator voltage V
(USB)
> 5.45 V 5 5.2 5.45 V
I
(DRV)
DRV Output current 10 mA
DRV Dropout voltage (V
(USB)
–
V
(DO_DRV)
I
(USB)
= 1A, V
(USB)
= 5 V, I
(DRV)
= 10 mA 450 mV
V
(DRV)
)
STATUS OUTPUT (STAT, INT)
V
OL
Low-level output saturation voltage I
O
= 10 mA, sink current 0.4 V
I
IH
High-level leakage current V
CHG
= V
PG
= 5 V 1 mA
PROTECTION
V
(UVLO)
IC active threshold voltage V
(USB)
rising 3.6 3.8 4 V
V
UVLO(HYS)
IC active hysteresis V
(USB)
falling from above V
(UVLO)
120 150 mV
Sleep-mode entry threshold, V
USB
-
V
(SLP)
2 V ≤ V
(BAT)
≤ V
(BATREG)
, V
USB
falling 0 40 100 mV
V
BAT
V
(SLP_EXIT)
Sleep-mode exit hysteresis 2 V ≤ V
(BAT)
≤ V
(BATREG)
40 100 175 mV
Deglitch time for supply rising
Rising voltage, 2-mV over drive, t
RISE
= 100 ns 30 ms
above V
SLP
+ V
SLP_EXIT
V
IN_DPM
–
Bad source detection threshold V
80 mV
Deglitch on bad source detection 32 ms
V
OVP
Input supply OVP threshold voltage USB, V
(USB)
Rising 6.3 6.5 6.7 V
V
OVP(HYS)
V
OVP
hysteresis Supply falling from V
(OVP)
100 mV
1.025 × 1.05 × 1.075 ×
V
(BOVP)
Battery OVP threshold voltage V
(BAT)
threshold over V
(OREG)
to turn off charger during charge V
V
BATREG
V
BATREG
V
BATREG
% of
VB
OVP
hysteresis Lower limit for V
(BAT)
falling from above V
(BOVP)
1
V
BATREG
V
BAT(UVLO)
Battery UVLO threshold voltage V
(BAT)
rising, 100 mV hysteresis 2.5 V
I
LIMIT
Cycle by Cycle current limit V
(SYS)
shorted 4.1 4.9 5.6 A
T
SHUTDWN
Thermal trip 165 °C
Thermal hysteresis 10 °C
T
REG
Thermal regulation threshold Charge current begins to cut off 120 °C
Safety timer accuracy –20% 20%
PWM
Internal top reverse blocking
I
(IN_LIMIT)
= 500 mA, Measured from V
(USB)
to PMIDU 95 175 mΩ
MOSFET on-resistance
Internal top N-channel Switching
Measured from PMIDU to SW 100 175 mΩ
MOSFET on-resistance
Internal bottom N-channel
Measured from SW to PGND 65 115 mΩ
MOSFET on-resistance
f
OSC
Oscillator frequency 1.35 1.50 1.65 MHz
D
MAX
Maximum duty cycle 95%
D
MIN
Minimum duty cycle 0%
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