Datasheet
bq24270
bq24271
www.ti.com
SLUSB10 –JUNE 2012
PIN FUNCTIONS
PIN NO. PIN NO.
bq24270 bq24271
PIN NAME I/O DESCRIPTION
YFF RGE YFF RGE
Ground terminal. Connect to the thermal pad (for QFN only) and the
AGND A1-A4 16, 21 A1-A4 16, 21 I
ground plane of the circuit.
USB Input Power Supply. USB is connected to the external DC supply
USB A5-A7 22 A5-A7 22 I (AC adapter or USB port). Bypass USB to PGND with at least a 1 μF
ceramic capacitor.
Bypass for internal supply. Bypass BYP to GND with at least a 0.1 µF
BYP B1-B4 20 B1-B4 20 O
ceramic capacitor.
Reverse Blocking MOSFET and High Side MOSFET Connection Point
for USB Input. Bypass PMID to GND with at least a 4.7μF ceramic
PMID B5-B7 23 B5-B7 23 O capacitor. Use caution when connecting an external load to PMID. The
PMID output is not current limited. Any short on PMID will result in
damage to the IC.
Inductor Connection. Connect to the switched side of the external
SW C1-C7 18 C1-C7 18 O
inductor.
D1-D7, E1, D1-D7, E1, Ground terminal. Connect to the thermal pad (for QFN only) and the
PGND 5, 15, 17 5, 15, 17 –
G7 G7 ground plane of the circuit.
D+ E2 2 – – I D+ and D- Connections for USB Input Adapter Detection. When a
charge cycle is initiated by the USB input, and a short is detected
between D+ and D-, the USB input current limit is set to 1.5 A. If a
D- E3 1 – – I
short is not detected, the USB100 mode is selected.
IC Hardware Disable Input. Drive CD high to place the bq24270 and
CD E4 24 E4 24 I
bq24271 in high-z mode. Drive CD low for normal operation.
I2C Interface Data. Connect SDA to the logic rail through a 10 kΩ
SDA E5 4 E5 4 I/O
resistor.
I2C Interface Clock. Connect SCL to the logic rail through a 10 kΩ
SCL E6 3 E6 3 I
resistor.
High Side MOSFET Gate Driver Supply. Connect a 0.01 µF ceramic
BOOT E7 19 E7 19 I capacitor (voltage rating > 10 V) from BOOT to SW to supply the gate
drive for the high side MOSFETs.
USB Source Detection Input. Drive PSEL high to indicate a USB
source is connected to the USB input. When PSEL is high, the IC starts
PSEL – – E2 2 I up with a 100mA input current limit for USB. Drive PSEL low to indicate
that an AC Adapter is connected to the USB input. When PSEL is low,
the IC starts up with a 1.5 A input current limit for USB.
System Voltage Sense and Charger FET Connection. Connect SYS to
SYS F1-F4 13, 14 F1-F4 13,14 I/O the system output at the output bulk capacitors. Bypass SYS locally
with 10 μF.
External Discharge MOSFET Gate Connection. BGATE drives an
external P-Channel MOSFET to provide a very low resistance
BGATE F5 10 F5 10 O discharge path. Connect BGATE to the gate of the external MOSFET.
BGATE is low in high impedance mode and when no input is
connected.
Status Output. INT is an open-drain output that signals charging status
and fault interrupts. INT pulls low during charging. INT is high
impedance when charging is complete or the charger is disabled.
INT F6 7 F6 7 O When a fault occurs, a 128 μs pulse is sent out as an interrupt for the
host. INT is enabled /disabled using the EN_STAT bit in the control
register. Connect INT to a logic rail through a 100 kΩ resistor to
communicate with the host processor.
Gate Drive Supply. DRV is the bias supply for the gate drive of the
internal MOSFETs. Bypass DRV to PGND with a 1 μF ceramic
DRV F7 6 F7 6 O capacitor. DRV may be used to drive external loads up to 10 mA. DRV
is active whenever the input is connected and V
USB
> V
UVLO
and V
USB
>
(V
BAT
+ V
SLP
)
Battery Connection. Connect to the positive terminal of the battery.
BAT G1-G4 11, 12 G1-G4 11, 12 I/O
Additionally, bypass BAT to GND with a 1μF capacitor.
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor
divider from DRV to GND. The NTC is connected from TS to GND. The
TS G5 9 G5 9 I TS function provides 4 thresholds for JEITA compatibility. TS faults are
reported by the I2C interface. See the NTC Monitor section for more
details on operation and selecting the resistor values.
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