Datasheet

Start-Up Short-Circuit Protection
Enable Function
Fault Indication
bq24380
bq24381
bq24382
SLUS805B – APRIL 2008 – REVISED MARCH 2009 ......................................................................................................................................................... www.ti.com
The bq2438x features overload current protection during start-up. The condition 1 in Figure 18 illustrates start-up
into an overload condition. If after the eight soft-start steps are complete, and the current limit is exceeded, the IC
initiates a short-circuit check timer (t
CHK(SC)
). During this check, the current is clamped to I
O(SC)
. If the 5-ms
t
CHK(SC)
timer expires and the current remains clamped by the current limit, the internal pass FET is turned off
using the soft-stop method, FAULT is pulled low and the t
REC(SC)
timer begins. Once the t
REC(SC)
timer expires,
FAULT becomes high impedance and the soft-start sequence restarts. The device repeats the start/fail sequence
until the overload condition is removed. Once the overload condition is removed, the current limit circuitry is
disabled and the device enters normal operation. Additionally, if the current is not limited after the completion of
the soft-start sequence, the t
CHK(SC)
timer does not start and the current limit circuitry is disabled for normal
operation.
The IC has an enable pin which is used to enable and disable the device. Connect the CE pin high to turn off the
internal pass FET. Connect the CE pin low to turn on the internal pass FET and enter the start-up routine. The
CE pin has an internal pulldown resistor and can be left unconnected. The FAULT pin is high impedance when
the CE pin is high.
The FAULT pin is an active-low, open-drain output. It is in a high-impedance state when operating conditions are
safe, or when the device is disabled by setting CE high. With CE low, the FAULT pin goes low whenever any of
these events occurs:
1. Output short-circuit at power-on
2. Input overvoltage
3. Battery overvoltage
4. IC overtemperature
See Figure 18 for an example of FAULT conditions during these events. Connect the FAULT pin to the desired
logic level voltage rail through a resistor between 1 k Ω and 50 k Ω .
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