Datasheet

V
IN
V
OUT
15
16
Q1
Q1
DRVE
DRVC
Q2
R
P
Q
EXT
R
P
V
IN
V
OUT
Q1
DRVE
16
DRVC
15
bq24450
SLUS929C –APRIL 2009– REVISED FEBRUARY 2012 www.ti.com
External Quasi-Darlington
I
MAX-CHG
range: 0.6A to 15A
Minimum ΔV: 1.2V
R
P
= (V
IN(MIN)
– 0.7 V) ÷ I
MAX-CHG
× h
FE1(MIN)
h
FE2(MIN)
P
D
= (V
IN(MAX)
– 0.7 V) ÷ (h
FE1
× h
FE2
) × I
MAX-CHG
– (I
MAX-CHG
)
2
÷ (h
FE1
× h
FE2
)
2
× R
P
C
COMP
= 0.22μF with 470Ω series resistor to GND
NPN Emitter-Follower
I
MAX-CHG
range: 25mA to 1000mA
Minimum ΔV: 2.7V
R
P
= (V
IN(MIN)
– V
OUT(MAX)
– 1.2 V) ÷ I
MAX-CHG
× h
FE(MIN)
P
D
= (V
IN(MAX)
– V
OUT
– 0.7 V) ÷ h
FE
× I
MAX-CHG
– (I
MAX-CHG
)
2
÷ (h
FE
)
2
× R
P
C
COMP
= 0.01μF to 0.047μF
DESIGN EXAMPLE
This section covers the design of a dual-level charger for a 6V 4Ah sealed lead-acid battery. The application is a
system where the battery is used in standby mode, and the load on the battery when it powers the system is
250mA (0.06C).
The battery parameters are (see References 1 and 2)
Final discharge voltage 1.75V per cell 5.25V V
TH
Float voltage 2.30V per cell 6.9V V
FLOAT
Voltage in boost mode 2.45V per cell 7.35V V
BOOST
Charge rate 0.05C to 0.3C Use 0.15C = 600 mA I
MAX-CHG
V
BAT(MIN)
4V
Trickle charge rate 10 mA
The charger is required to operate from a supply voltage of 9V to 13V. Therefore, the minimum input to output
differential is 1.65V. To block reverse current from the battery to the input supply use a blocking diode as in
Figure 8. This leaves only 0.65V as the differential across the external transistor, forcing the use of the
Common-Emitter PNP topology.
Figure 10 is the schematic for this charger (from Figure 8, with the pass transistor topology changed), with the
remaining task being the calculation of all the component values.
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