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SLUS491 – JULY 2001

   

   

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FEATURES

Multifunction High-Accuracy Coulometric

Charge and Discharge Counter

D Ideal for Portable Applications With

Nonremovable Rechargeable Battery Pack

D Resolves Signals Less Than 12.5 µV

D Internal Offset Calibration Improves Accuracy

D 128 Bytes of General-Purpose RAM

D Internal Temperature Sensor Eliminates the

Need for an External Thermistor

D High-Accuracy Internal Timebase Eliminates

External Crystal Oscillator

D Low Power Consumption:

– Operating: < 80 µA

– Sleep: < 10 µA

D Single-Wire HDQ Serial Interface

D Packaging: 8-Lead TSSOP

DESCRIPTION

The bq26231 is a low-cost charge/discharge counter

peripheral in an 8-pin TSSOP. It works with an intelligent

host controller, providing state-of-charge information

for rechargeable Li-Ion, Li-Pol, or NiMH batteries. The

bq26231 measures the voltage drop across a low-value

series sense resistor between the negative terminal of

the battery and the battery pack ground contact. By

using the accumulated counts in the charge, discharge,

and self-discharge registers, an intelligent host

controller can determine battery state-of-charge

information. To improve accuracy, an offset count

responsible for the register maintenance by resetting

the charge in/out and self-discharge registers as

needed.

The bq26231 features 13 bytes of registers, which

contain the capacity monitoring and status information.

The RBI input operates from an external power storage

source such as a capacitor or a series cell in the battery

pack, providing register nonvolatility for periods when

the battery is shorted to ground or when the battery

charge state is not sufficient to operate the bq26231.

During this mode, the register backup current is less

than 100 nA. Packaged in an 8-pin TSSOP, the

bq26231 is small enough to fit in the crevice between

two A-size cells or within the width of a prismatic cell.

VCC

VSS

HDQ

SR1

SR2

RBI

PW PACKAGE

(TOP VIEW)

AVAILABLE OPTIONS

PACKAGE

OPR

8-Lead TSSOP

(PW)

–20°C to 70°C bq26231PW

        

         

       

   

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (20 pages)

PAGE 1
SLUS491 – JULY 2001 FEATURES D Multifunction High-Accuracy Coulometric D D D D D D D D D Charge and Discharge Counter Ideal for Portable Applications With Nonremovable Rechargeable Battery Pack Resolves Signals Less Than 12.
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SLUS491 – JULY 2001 functional block diagram SR1 Differential Dynamically Balanced VFC SR2 Calibration and Power Control System I/O and Control HDQ Registers RBI VCC TemperatureCompensated Precision Oscillator Bandgap Voltage Reference Timer Temperature Sensor VSS Terminal Functions TERMINAL 2 NAME NO. NC 1 VCC 2 I/O DESCRIPTION No connect. This pin must be left floating.
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SLUS491 – JULY 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VCC with respect to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V Input voltage: HDQ (all with respect to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V RBI, SR1, and SR2 (with respect to VSS) . . . . . . . . . . . . . . . . . . . . .
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SLUS491 – JULY 2001 standard serial communication timing specification over recommended operating temperature and supply voltage, refer to Figure 1 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT µs t(CYCH) t(CYCB) Cycle time, host to bq26231 (write) 190 Cycle time, bq26231 to host (read) 190 t(STRH) t(STRB) Start hold, host to bq26231 (write) 5 ns Start hold, bq26231 to host (read) 32 µs t(DSU) t(DSUB) Data setup (write) 50 µs Data setup (read) 50 µs t(
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SLUS491 – JULY 2001 detailed description SR1–SR2 current sense inputs The bq26231 interprets charge and discharge activity by monitoring and integrating the voltage drop V(SR) across pins SR1 and SR2. The SR1 input connects to the sense resistor and the negative terminal of the battery. The SR2 input connects to the sense resistor and the negative terminal of the pack. V(SR1) < V(SR2) indicates discharge, and V(SR1) > V(SR2) indicates charge.
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SLUS491 – JULY 2001 APPLICATION INFORMATION VCC U1 1 2 BAT+ R5 100 Ω R6 100 Ω HDQ C3 0.1 µF 3 4 NC VCC VSS HDQ NC SR1 SR2 RBI 8 R2 100 kΩ 7 BAT– C1 0.01 µF 6 R1 0.02 Ω 5 PACK– D2 5.6 V bq26231 R3 100 kΩ C2 0.01 µF RBI C4 0.1 µF D1 1N914 R4 1 MΩ Figure 2. Typical Application functional description The bq26231 measures the voltage drop across a low-value series current sense resistor between the SR1 and SR2 pins using a voltage-to-frequency converter.
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SLUS491 – JULY 2001 APPLICATION INFORMATION functional description (continued) charge and discharge count operation Table 2 shows the main counters and registers of the bq26231. The bq26231 accumulates charge and discharge counts into two main count registers the discharge count register (DCR) and the charge count register (CCR).
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SLUS491 – JULY 2001 APPLICATION INFORMATION charge and discharge count operation (continued) Figure 3 shows the bq26231 register address map. The bq26231 uses the upper 13 locations. The remaining memory can store user-specific information such as chemistry, serial number, and manufacturing date.
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SLUS491 – JULY 2001 APPLICATION INFORMATION CLEAR register The host system is responsible for register maintenance. To facilitate this maintenance, the bq26231 has a clear register (TMP/CLR) designed to reset the specific counter or register pair to zero. The host system clears a register by writing the corresponding register bit to 1. When the bq26231 completes the reset, the corresponding bit in the TMP/CLR register is automatically reset to 0, which saves the host an extra write/read cycle.
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SLUS491 – JULY 2001 APPLICATION INFORMATION communicating with the bq26231 (continued) The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq26231 taking the HDQ pin to a logic-low state for a period t(STRH,B). The next section is the actual data transmission, where the data should be valid by a period t(DSU,B) after the negative edge used to start communication.
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SLUS491 – JULY 2001 APPLICATION INFORMATION bq26231 command and status registers The bq26231 command and status registers are listed and described in Table 4. command (CMDR) The write-only command register is accessed when the bq26231 has received eight contiguous valid command bits. The command register contains two fields: D W/R D Command address The W/R bit of the command register is used to select whether the received command is for a read or a write function.
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SLUS491 – JULY 2001 APPLICATION INFORMATION command (CMDR) (continued) The lower seven-bit field of CMDR contains the address portion of the register to be accessed. CDMR BITS 7 6 5 4 3 2 1 0 – AD6 AD5 AD4 AD3 AD2 AD1 AD0 discharge count registers (DCRH/DCRL) The DCRH high-byte register (address = 7F hex) and the DCRL low-byte register (address = 7E hex) contain the count of the discharge and are incremented whenever V(SR1) < V(SR2).
PAGE 13
SLUS491 – JULY 2001 APPLICATION INFORMATION mode/wake-up enable register The Mode/WOE register (address = 75 hex) contains the calibration and wake-up enable information, and the STC and STD bits as described below. The override DQ (OVRDQ) bit (bit 7) is used to override the requirement for HDQ to be low before initiating V(OS) calibration. This bit is normally set to zero. If OVRDQ is written to one, the bq26231 begins offset calibration when |V(SR)| < V(WOE) where HDQ = Don’t care.
PAGE 14
SLUS491 – JULY 2001 APPLICATION INFORMATION mode/wake-up enable register (continued) The WOE 3–1 locations are MODE/WOE BITS 7 6 5 4 3 2 1 0 – – – – WOE3 WOE2 WOE1 – where WOE3–1 is determined by dividing 3.84 mV by the value in WOE. NOTE: Bit 0 of the MODE/WOE register is reserved and must remain 0. Table 5. WOE Thresholds WOE3–1 (hex) 0 V(WOE) (mV) N/A 1 3.840 2 1.920 3 1.280 4 0.960 5 0.768 6 0.640 7 (default after POR) 0.
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SLUS491 – JULY 2001 APPLICATION INFORMATION temperature and clear register (continued) The clear bit locations are TMP/CLR BITS 7 6 5 4 3 2 1 0 – – – CTC DTC SCR CCR DCR Where: The CTC bit (bit 4) resets both the CTCH and CTCL registers and the STC bit to 0. The DTC bit (bit 3) resets both the DTCH and DTCL registers and the STD bit to 0. The SCR bit (bit 2) resets both the SCRH and SCRL registers to 0. The CCR bit (bit 1) resets both the CCRH and CCRL registers to 0.
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SLUS491 – JULY 2001 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°–ā8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. 16 All linear dimensions are in millimeters. This drawing is subject to change without notice.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device BQ26231PWR Package Package Pins Type Drawing TSSOP PW 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 7.0 3.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ26231PWR TSSOP PW 8 2000 346.0 346.0 29.
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