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FEATURES APPLICATIONS

DESCRIPTION

bq27000 , bq27200

SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006

SINGLE CELL Li-Ion AND Li-Pol BATTERY GAS GAUGE IC FOR PORTABLE

APPLICATIONS (bqJUNIOR)

• PDA

• HDQ (bq27000) or I

C (bq27200)

Communication

• Smart Phones

• MP3 Players

• Reports Accurate Time-to-Empty With

Measured Load and Historical Maximum and

• Digital Cameras

Standby Loads

• Internet Appliances

• Reports Temperature, Voltage, and Current

• Handheld Devices

• High Accuracy Charge and Discharge Current

Integration with Automatic Offset Calibration

• Requires No User Calibration

The bqJUNIOR™ series are highly accurate

stand-alone single-cell Li-Ion and Li-Pol battery

• Programmable Input/Output Port

capacity monitoring and reporting devices targeted at

• Internal User EEPROM Configuration Memory

space-limited, portable applications. The IC monitors

• Automatic Capacity Reduction With Age

a voltage drop across a small current sense resistor

connected in series with the battery to determine

• Stable Oscillator Without External

charge and discharge activity of the battery.

Components

Compensations for battery temperature,

• Dynamic End-of-Discharge Detection Delay to

self-discharge, and discharge rate are applied to the

Allow Use in a High-Dynamic Load

capacity measurments to provide available

Environment

time-to-empty information across a wide range of

• Automatic Sleep Mode When Communication operating conditions. Battery capacity is automatically

recalibrated, or learned, in the course of a discharge

Lines are Low

cycle from full to empty. Internal registers include

• Available in a Small 3 mm x 4 mm QFN

current, capacity, time-to-empty, state-of-charge, cell

Package

temperature and voltage, status, and more.

• Five Low-Power Operating Modes

The bqJUNIOR can operate directly from single-cell

– Active: < 90 µA

Li-Ion and Li-Pol batteries and communicates to the

– Sleep: < 2.5 µA

system over a HDQ one-wire or I

C serial interface.

– Ship: < 2 µA (bq27000 only)

– Hibernate: < 1.5 µA

– Data Retention: < 20 nA

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

bqJUNIOR is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
bq27000, bq27200 www.ti.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 TYPICAL APPLICATION PACK+ PGM TP R3 1 kΩ 1 C4 0.1 µF PGM 10 + R4 10 kΩ Li-Ion or Li-Pol bq27000DRK 2 VCC 3 VSS GPIO 9 R1 1 kΩ SRP 8 C3 0.1 µF C1 0.1 µF 4 R7 100 Ω RBI D/C RS 0.02 Ω SRN 7 R2 1 kΩ R8 100 Ω HDQ 5 HDQ D2 5.6 V BAT 6 C3 0.1 µF C2 0.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT VCC Supply voltage 2.6 4.5 V TA Operating free-air temperature –20 70 °C –100 100 mV Input voltage, SRP and SRN with respect to VSS ELECTRICAL CHARACTERISTICS over operating free-air temperature range and supply voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GENERAL ICC(VCC) Active current 52 90 ICC(SLP) Sleep current 1.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range and supply voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STANDARD HDQ SERIAL COMMUNICATION TIMING (bq27000 only) t(B) Break timing t(BR) Break recovery 190 40 t(CYCH) Host bit window 190 t(HW1) Host sends 1 0.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 TIMING DIAGRAMS t(BR) t(B) (a) Break and Break Recovery t(HW1) t(DW1) t(DW0) t(HW0) t(CYCH) t(CYCD) (b) Host Transmitted Bit Break (c) bqJUNIOR Transmitted Bit 1-Bit R/W 7−Bit Address 8−Bit Data t(RSPS) UDG−03039 (d) bqJUNIOR to Host Response Figure 1.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 TIMING DIAGRAMS (continued) BQ27000 DRK PACKAGE (BOTTOM VIEW) BQ27200 DRK PACKAGE (BOTTOM VIEW) RBI VCC VSS D/C HDQ RBI VCC VSS SCL SDA 1 2 3 4 5 1 2 3 4 5 bq27000DRK bq27200DRK 11 10 9 11 8 PGM GPIO SRP 7 6 10 SRN BAT 9 PGM GPIO SRP DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME I/O DESCRIPTION bq27000 bq27200 BAT 6 6 I Battery voltage sense input D/C 4 - - Do not connect.
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bq27000, bq27200 www.ti.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 FUNCTIONAL DESCRIPTION (continued) Figure 3 shows a typical application circuit. Differential sense of the voltage across the current sense resistor, RS, improves device performance, leading to an improvement in reported time-to-empty accuracy.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 FUNCTIONAL DESCRIPTION (continued) Offset Calibration The offset voltage of the DSCC measurement must be very low to be able to measure small signal levels accurately. The bqJUNIOR provides an auto-calibration feature to cancel the internal voltage offset error across SRP and SRN for maximum charge measurement accuracy. NO CALIBRATION IS REQUIRED.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 FUNCTIONAL DESCRIPTION (continued) RBI Input The RBI input pin is used with an external capacitor to provide backup potential to the internal registers when VCC drops below V(POR). VCC is output on RBI when VCC is above V(POR), charging the capacitor. An optional 1 MΩ resistor can be added from the RBI pin to VCC.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 FUNCTIONAL DESCRIPTION (continued) A learning cycle can be disqualified by any of the following conditions: 1. Cold temperature: Temperature ≤ TCOMP[3:0] (°C) when the EDV1 threshold voltage is reached. 2. Light load: A capacity learning cycle is disqualified if average current is less than or equal to 2 times the initial standby load when the EDV1 threshold voltage is reached. 3.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 FUNCTIONAL DESCRIPTION (continued) Table 1.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 APPLICATION INFORMATION Control and MODE Registers (CTRL/MODE) — Address 0x00/0x01 The device control register is used by the host system to request special operations by the bqJUNIOR. The highest priority command set in the MODE register is performed when the host writes data 0xA9 or 0x56 as indicated to the control register. The CTRL register is cleared when the command is accepted.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 that WRTNAC (bit 5) has higher priority than DONE (bit 4); PRST (bit 3) has higher priority than FRST (bit 1), and so on. Only the highest priority mode set is enabled each time the CTRL register is written with data 0xA9, and the firmware clears all other mode bits and the CTRL register when that action is complete.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 CI Capacity Inaccurate flag. A 1 indicates that the firmware has not been through a valid learning cycle and is basing all calculations on initial design values programmed into EEPROM or that there have been at least 32 cycle-count increments since the last learning cycle. This bit is cleared only on a LMD update following a learning cycle. This bit is set to 1 on a full reset.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 Last Measured Discharge Registers (LMDL/LMDH) — Address 0x12/0x13 Last measured discharge is the measured discharge capacity of the battery from full to empty. LMD is updated on a valid learning cycle, which occurs when the battery reaches the EDV1 level while the VDQ bit is set. It is used with NAC to calculate Relative State-Of-Charge (RSOC). The host system has read-only access to this register pair.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 Max Load Current Registers (MLIL/MLIH) — Address 0x1E/0x1F This register pair reports the measured maximum load current through sense resistor. The max load current is an adaptive measurement of the maximum load conditions. If the measured current is ever greater than the initial Max Load Current programmed in EEPROM, the register pair updates to the new current.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 Cycle Count Since Learning Cycle Registers (CYCLL/CYCLH) — Address 0x28/0x29 CYCL is the cycle count since the last learning cycle. Each count indicates an increment of CYCT since there was a learning cycle. This register is cleared every time there is a learning cycle. When this count reaches 32, it forces the CI flag in FLAGS to a 1. The host system has read-only access to this register pair.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 Scaled EDVF Threshold (SEDVF) — Address 0x77 This register contains the scaled value of the threshold for zero battery capacity. To calculate the value to program, use the following equation: SEDVF = Design EDVF(mV)/8 – 256 Scaled EDV1 Threshold (SEDV1) — Address 0x78 This register contains the scaled value of the voltage when the battery has 6.25% remaining capacity.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 TAPER[7] should be set to 1 to enable the automatic aging of the LMD full capacity value. If this feature is enabled, LMD is reduced by Design Capacity/1024 every time CYCL increments by 2 and every time that a cumulative NAC self-discharge estimate reduction of 1.56% has been made without charging the battery to full. If TAPER[7] is set to 0, there is no LMD reduction with cycle count or self-discharge.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 The user can optionally use this byte in the EEPROM as an identification byte. If so used, the user should ignore the values in MLI and MLTTE registers. Discharge Rate Compensation Constants (DCOMP) — Address 0x7E This register is used to set the compensation coefficients for discharge rate. These coefficients are applied to the nominal available charge to more accurately predict capacity at high discharge rates.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 Temperature compensation, TCMP, is computed from these coefficients as follows: TCMP = TCGN * ILMD(273 + TOFF - T)/4 where T is the temperature in °K and TCMP ≥ 0. CACT is then computed as follows: CACT = CACD – TCMP If PKCFG[0] = 1, the device assumes a fixed value of 0x7C for TCOMP, giving a temperature compensation gain of 0.68% DC/°C with an offset of 12°C.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 Active Mode During normal operation, the device is in active mode, which corresponds to the highest power consumption. Normal gas gauging is performed in this mode. If system requirements mandate that bqJUNIOR should not enter Sleep or Ship modes, then an external pullup resistor from VCC to keep HDQ or CLK and DTA at a logic 1 is required on the bqJUNIOR side of the system.
PAGE 24
bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 Host enables E2PROM programming mode. Write data 0xDD to address 0x6E Host writes data in addresses 0x76 − 0x7F Host reads data address 0x76 21−V pulse applied to PROG pin for 50 ms Host increments address and reads Programmed 0x7F? No Yes Write data 0x00 to address 0x6E UDG−04099 Figure 6. EEPROM Programming Flow It is not required that addresses 0x76 — 0x7F be programmed at the same time or in any particular order.
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 If a communication timeout occurs (for example, if the host waits longer than T(RSPS) for the bq27000 to respond) or if this is the first access command, then a BREAK should be sent by the host. The host may then resend the command. The bq27000 detects a BREAK when the HDQ pin is driven to a logic-low state for a time T(B) or greater. The HDQ pin then returns to its normal ready-high logic state for a time T(BR).
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bq27000, bq27200 www.ti.com SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 Communicating with the bq27200 (I2C interface) The bq27200 supports the standard I2C read, incremental read, quick read, and one byte write functions. The 7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The 8-bit device address is therefore 0xAA or 0xAB for write or read, respectively.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ27000DRKR VSON DRK 10 3000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q2 BQ27200DRKR VSON DRK 10 3000 330.0 12.4 3.3 4.3 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ27000DRKR VSON DRK 10 3000 338.1 338.1 20.6 BQ27200DRKR VSON DRK 10 3000 338.1 338.1 20.
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