Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - battery management Surge/undervoltage protection Li-Ion, Li-Po TSSOP 30 Surface-mou

LDO+

Reset

SMBus

HDQ

UART

Pack+

Pack –

Discharge/Charge/

PrechargeFETs

2-TierOvercurrent

Protection

2KBytesof

DataFlash

Fuse

Watchdog&

Protection Timing

Cell Balancing Drive

SystemInterface SystemInterface

32.768kHz

16DigGPIO&Peripherals

8DigGPIOor AnalogGPI

2.5V

NchFET Drive

(ChargePumps)

RAMConfiguration,Status

andControlRegisters

24Kx22Program

Flash

2KBytes

ofRAM

6Kx22

MaskROM

Cell, Bat and Pack

Voltage Translation

Precharge

Control

Host Interface UART

& Data Management

TOUT andLEDOUT

PowerSupport

Reset

AnalogOutputDrive

OscillatorandPLL

Internal

Only

StandardDelta-Sigma A-to-DConverter

IntegratingDelta-Sigma A-to-DConverter

bq29330

www.ti.com

SLUS673E –SEPTEMBER 2005–REVISED MARCH 2012

2-SERIES, 3-SERIES, AND 4-SERIES CELL LITHIUM-ION OR

LITHIUM-POLYMER BATTERY PROTECTION AFE

Check for Samples: bq29330

FEATURES

• 2-Series, 3-Series, or 4-Series Cell Protection • NMOS FET Drive for Charge and Discharge

Control FETs

• Can Directly Interface with the bq803x-Based • Host Control can Initiate Sleep and Ship Power

Gas Gauge Family Modes

• Watchdog and POR for the Host • Integrated 2.5-V, 16-mA LDO

• Provides Individual Cell Voltages and Battery • Integrated 3.3-V, 25-mA LDO

Voltage to Battery Management Host

• Supply Voltage Range from 4.5 V to 28 V

• Capable of Operation With 5-mΩ Sense

• Low Supply Current of 100 μA Typical

Resistor Integrated Cell Balancing Drive

• I

C Compatible User Interface Allows Access APPLICATIONS

to Battery Information

• Notebook Computers

• Programmable Threshold and Delay for

• Medical and Test Equipment

Overload Short Circuit in Discharge and Short

• Instrumentation and Measurement Systems

Circuit in Charge

DESCRIPTION

The bq29330 is a 2-series, 3-series, and 4-series cell lithium-ion battery pack full-protection analog front end

(AFE) IC that incorporates a 2.5-V, 16-mA and 3.3-V, 25-mA low dropout regulator (LDO). The bq29330 also

integrates an I

C-compatible interface to extract battery parameters such as battery voltage, individual cell

voltages, and control output status. Other parameters such as current protection thresholds and delays can also

be programmed into the bq29330 to increase the flexibility of the battery management system.

SYSTEM DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

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bq29330 www.ti.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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bq29330 www.ti.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com PIN FUNCTIONS (continued) PIN NAME DESCRIPTION DBT NO. RSM NO. WDI 26 24 Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog clock.
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bq29330 www.ti.com SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 SAFETY STATE DIAGRAM LEGEND: UVLO = Undervoltage Lock Out KEY: Disabled = OFF and cannot be changed via firmware Enabled= Can be changed by firmware No Power Supply Power Supply to PACK Power Supply to PACK UVLO Mode CHG: OFF DSG: OFF ZVCHG: OFF VREG: OFF RST: HIGH I2 C: Disabled Current Protection: Disabled VCELL: Disabled Watchdog: Disabled Therm, Output: Disabled Internal VLED < 2.3 V Internal VLED> 2.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) bq29330 Supply voltage range Input voltage range Output voltage range (VCC, BAT) –0.3 to 34 (VC1, VC2, VC3, VC4, PACK, PMS) –0.3 to 34 (VC5) –0.3 to 1.0 (SRP, SRN) –1.0 to 1.0 (VC1 to VC2, VC2 to VC3, VC3 to VC4, VC4 to VC5) –0.3 to 8.5 (WDI, SCLK, SDATA) –0.3 to 8.5 (DSG,CHG) –0.3 to BAT (ZVCHG) –0.3 to 34 (GPOD) –0.
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bq29330 www.ti.com SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS SUPPLY CURRENT, TA = 25°C, CREG = 1 μF, CL = 2.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) CELL VOLTAGE MONITOR, TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V (unless otherwise noted) PARAMETER V(CELLOUT) REF MIN TYP MAX VCn – VCn+1 = 0 V, 8 V ≤ VDD ≤ 25 V TEST CONDITIONS 0.950 0.975 1 VCn – VCn+1 = 4.5 V, 8 V ≤ VDD ≤ 25 V 0.275 0.3 0.325 Mode (1) , 8 V ≤ VDD ≤ 25 V UNIT V –1% 0.
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bq29330 www.ti.com SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS (Continued) FET DRIVE CIRCUIT, TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V (unless otherwise noted) PARAMETER VO(FETON) V(ZCHG) VO(FETOF Output voltage, charge, and discharge FETs on ZVCHG clamp voltage TEST CONDITIONS VO(FETOND) = V(DSG) – Vpack VGS connect 10 MΩ TA = 25°C VO(FETONC) = V(CHG) – VBAT VGS connect 10 MΩ TA = 25°C TA = –40°C to 110°C TA = –40°C to 110°C BAT = 4.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com AC TIMING REQUIREMENTS (I2C compatible serial interface) TA = 25°C, CREG = 1 μF, VCC or BAT = 14 V (unless otherwise noted) PARAMETER MIN MAX UNIT ns tr SCLK, SDATA rise time 1000 tf SCLK, SDATA fall time 300 tw(H) SCLK pulse width high 4 μs tw(L) SCLK pulse width low 4.7 μs tsu(STA) Setup time for start condition 4.
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bq29330 www.ti.com SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 FUNCTIONAL DESCRIPTION LOW DROP OUTPUT REGULATOR (LEDOUT) The inputs for this regulator can be derived from the VCC or BAT terminals. The output is a fixed voltage of typically 3.3 V with the minimum output capacitance for stable operation of 2.2 μF and is also internally current limited. This output is used for LED drive, power supply source for REG (2.5 V) and bq29330 internal circuit.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com OVERLOAD, SHORT CIRCUIT IN CHARGE AND SHORT CIRCUIT IN DISCHARGE RESPONSE When an overload, short circuit in charge, or short circuit in discharge fault is detected, the FETs are turned off. The STATUS (b0…b3) register reports the details of overload, short circuit in charge or short-circuit discharge. The respective STATUS (b0…b3) bits are set to 1 and the XALERT output is triggered.
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bq29330 www.ti.com SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 Step 5 Calculate the actual offset value where: VOS(ACT) = (V(OUTR) – VREF) / (1 + KACT) Step 6 Calibrated cell voltage is calculated by: VCn – VC(n+1) = { VREF + (1 + KACT ) × VOS(ACT) – V(CELLOUT)}/KACT = {VOUT(4-5) – V(CELLOUT)}/KACT To seek greater accuracy, it is better to measure VOS(ACT) for each cell voltage. Set CAL1=0, CAL0=0, CELL1=0, CELL0=1, VMEN=1. Set CAL1=0, CAL0=0, CELL1=1, CELL0=0, VMEN=1.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com LATCH CLEAR (LTCLR) When a protection fault occurs, the state is latched. To clear the fault flag, toggle (from 0, set 1, then reset to 0) the LTCLR bit in the STATE_CONTROL register (bit 7). The OL, SCC, SCD, and WDF bits are unlatched by this function. The FETs can now be controlled by programming the OUTPUT_CONTROL register, and the XALERT output can be cleared by reading the STATUS register.
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bq29330 www.ti.com SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 If the host clock oscillation is started after the reset, the bq29330 still has the WDF flag set until it is cleared. See the LTCLR section for further details on clearing the fault flags. During Sleep mode, the watchdog function is not disabled.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com REG Output Normal Operation tWDWT tDWTINIT(500 ms) tDWTINIT(500 ms) REG Output tRST WDI Input XALERT CHG, DSG, and ZVCHG = OFF FET Control Access by Host WDRST = L REG Output Normal Operation tWDWT tDWTINIT(500 ms) tDWTINIT(500 ms) REG Output tRST tRST tRST WDI Input XALERT CHG, DSG, and ZVCHG = OFF FET Control Access by Host WDRST = H Figure 4.
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bq29330 www.ti.com SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 PRECHARGE AND 0 V CHARGING The bq29330 supports both a charger that has a precharge mode and one that does not. The bq29330 also supports charging even when the battery falls to 0 V. In order to charge, the charge FET (CHG) must be turned on to create a current path. When the VBAT is ~0 V, the V(PACK) is as low as the battery voltage. In this case, the supply voltage for the device is too low to operate.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com … … SCLK SDATA A6 A5 … A4 … A0 R/W ACK 0 Start R7 R6 R5 … … R0 D7 ACK 0 D6 … D0 D5 0 Slave Address ACK 0 Data Register Address Stop Note: Slave = bq29330 Figure 5.
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bq29330 www.ti.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com OUTPUT_ CONTROL b1 (DSG): This bit controls the external discharge FET. 0= Discharge FET is off and is controlled by the system host (default). 1= Discharge FET is on, and the bq29330 is in normal operating mode. OUTPUT_ CONTROL b2 (CHG): This bit controls the external charge FET. 0= Charge FET is off, and is controlled by the system host (default). 1= Charge FET is on, and the bq29330 is in normal operating mode.
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bq29330 www.ti.com SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 FUNCTION_CONTROL : Function control register 7 0 6 0 FUNCTION_CTL REGISTER (0x03) 4 3 0 TOUT 5 0 2 BAT 1 PACK 0 VMEN The FUNCTION_CONTROL register enables and disables features of the bq29330. FUNCTION_CONTROL b0 (VMEN): This bit enables or disables the cell and battery voltage monitoring function. 0= Disable voltage monitoring (default). CELL output is pulled down to GND level.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.
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bq29330 www.ti.com SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 OLD: Overload Delay time configuration register 7 0 6 0 OLD REGISTER (0x07) 4 3 0 OLD3 5 0 2 OLD2 1 OLD1 0 OLD0 OLD(b3–b0): These four bits select the value of the delay time for overload with a default of 0000.
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bq29330 SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com REVISION HISTORY Changes from Original (September 2005) to Revision A Page • Changed package name From: SSOP(DBT) To: TSSOP(DBT) in the Ordering Information Table .................................... 2 • Changed the SCLK pin description From: Open-drain bi-directional serial interface clock with internal 10-kΩ pullup to VREG To: Open-drain serial interface clock with internal 10-kΩ pullup to VREG .......................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device BQ29330DBTR Package Package Pins Type Drawing TSSOP DBT 30 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ29330DBTR TSSOP DBT 30 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.