Datasheet

t
su(STA)
SCLK
SDATA
SCLK
SDATA
SCLK
SDATA
t
w(H)
t
w(L)
t
f
t
r
t
r
t
f
Start
Condition
SDA
Input
SDA
Change
Stop
Condition
t
h(STA)
t
h(DAT)
t
su(DAT)
t
h(ch)
Start Condition
t
v
1 2 3 7 8 9
MSB
ACK
Stop Condition
t
su(STOP)
1 2 3 7 8 9
MSB
ACK
t
su(BUF)
bq29330
SLUS673E –SEPTEMBER 2005–REVISED MARCH 2012 www.ti.com
AC TIMING REQUIREMENTS (I
2
C compatible serial interface)
T
A
= 25°C, CREG = 1 μF, VCC or BAT = 14 V (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
r
SCLK, SDATA rise time 1000 ns
t
f
SCLK, SDATA fall time 300 ns
t
w(H)
SCLK pulse width high 4 μs
t
w(L)
SCLK pulse width low 4.7 μs
t
su(STA)
Setup time for start condition 4.7 μs
t
h(STA)
Start condition hold time after which first clock pulse is generated 4 μs
t
su(DAT)
Data setup time 250 ns
t
h(DAT)
Data hold time 0 μs
t
su(STOP)
Setup time for Stop condition 4 μs
t
su(BUF)
Time the bus must be free before new transmission can start 4.7 μs
t
v
Clock low to data out valid 900 ns
t
h(CH)
Data out hold time after clock low 10 ns
f
SCL
Clock frequency 0 100 kHz
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