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bq29330
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SLUS673E –SEPTEMBER 2005–REVISED MARCH 2012
BIT MAP
NAME ADDR TYPE
B7 B6 B5 B4 B3 B2 B1 B0
STATUS 0x00 R 0 0 0 ZV WDF OL SCC SCD
OUTPUT_ CONTROL 0x01 R/W 0 0 PMS_CHG GPOD XZV CHG DSG LTCLR
STATE_ CONTROL 0x02 R/W 0 0 0 RSNS WDRST WDDIS SHIP SLEEP
FUNCTION_ CONTROL 0x03 R/W 0 0 0 0 TOUT BAT PACK VMEN
CELL _SEL 0x04 R/W CB3 CB2 CB1 CB0 CAL1 CAL0 CELL1 CELL0
OLV 0x05 R/W 0 0 0 OLV4 OLV3 OLV2 OLV1 OLV0
OLD 0x06 R/W 0 0 0 0 OLD3 OLD2 OLD1 OLD0
SCC 0x07 R/W SCCD3 SCCD2 SCCD1 SCCD0 SCCV3 SCCV2 SCCV1 SCCV0
SCD 0x08 R/W SCDD3 SCDD2 SCDD1 SCDD0 SCDV3 SCDV2 SCDV1 SCDV0
STATUS: Status register
STATUS REGISTER (0x00)
7 6 5 4 3 2 1 0
0 0 0 ZV WDF OL SCC SCD
The STATUS register provides information about the current state of the bq29330.
STATUS b0 (SCD): This bit indicates a short circuit in discharge condition.
0 = Voltage below the short circuit in discharge threshold (default).
1 = Voltage greater than or equal to the short circuit in discharge threshold.
STATUS b1 (SCC): This bit indicates a short circuit in charge condition in the charge direction.
0 = Voltage below the short circuit in charge threshold (default).
1 = Voltage greater than or equal to the short circuit in charge threshold.
STATUS b2 (OL): This bit indicates an overload condition.
0 = Voltage less than or equal to the overload threshold (default).
1 = Voltage greater than overload threshold.
STATUS b3 (WDF): This bit indicates a watchdog fault condition has occurred.
0 = 32-kHz oscillation is normal (default).
1 = 32-kHz oscillation stopped or not started, and the watchdog has timed out.
STATUS b4 (ZV): This bit indicates ZVCHG output is clamped.
0 = ZVCHG pin is not clamped (default).
1 = ZVCHG pin is clamped.
STATUS b5, b6, b7: Reserved
OUTPUT_CONTROL : Output control register
OUTPUT_CONTROL REGISTER (0x01)
7 6 5 4 3 2 1 0
0 0 PMS_CHG GPOD XZV CHG DSG LTCLR
The OUTPUT_CONTROL register controls the outputs of the bq29330 and can show the state of the external pin
corresponding to the control.
OUTPUT_ CONTROL b0 (LTCLR): When a fault is latched, this bit releases the fault latch when toggled from 0
to 1 and back to 0 (default =0).
0 = (default)
0->1 ->0 clears the fault latches, allowing STATUS to be cleared on its next read.
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