Datasheet

P3/SDA

P4/SCL

P5/HDQ

P6/TS

BAT

VEN

REGIN

REG25

SRN

SRP

VSS

bq34z100

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SLUSAU1B –MAY 2012–REVISED DECEMBER 2012

PIN DETAILS

PINOUT DIAGRAM

Figure 1. bq34z100 Pinout Diagram

PIN DESCRIPTIONS

Table 1. bq34z100 External Pin Functions

PIN NAME TYPE

(1)

DESCRIPTION

NUMBER

P2 1 O LED 2 or Not Used (connect to Vss)

VEN 2 O Active High Voltage Translation Enable. This signal is optionally used to switch the input voltage

divider on/off to reduce the power consumption (typ 45 µA) of the divider network.

P1 3 O LED 1 or Not Used (connect to Vss). This pin is also used to drive an LED for single-LED mode.

Use a small signal N-FET (Q1) in series with the LED as shown on Figure 9.

BAT 4 I Translated Battery Voltage Input

CE 5 I Chip Enable. Internal LDO is disconnected from REGIN when driven low.

REGIN 6 P Internal integrated LDO input. Decouple with a 0.1-µF ceramic capacitor to Vss.

REG25 7 P 2.5-V Output voltage of the internal integrated LDO. Decouple with 1-µF ceramic capacitor to Vss

VSS 8 P Device ground

SRP 9 I Analog input pin connected to the internal coulomb-counter peripheral for integrating a small

voltage between SRP and SRN where SRP is nearest the BAT– connection.

SRN 10 I Analog input pin connected to the internal coulomb-counter peripheral for integrating a small

voltage between SRP and SRN where SRN is nearest the PACK– connection.

P6/TS 11 I Pack thermistor voltage sense (use 103AT-type thermistor)

P5/HDQ 12 I/O Open drain HDQ Serial communication line (slave)

P4/SCL 13 I Slave I

C serial communication clock input. Use with a 10-K pull-up resistor (typical). Also used

for LED 4 in the four-LED mode.

P3/SDA 14 I/O Open drain slave I

C serial communication data line. Use with a 10-kΩ pull-up resistor (typical).

Also used for LED 3 in the four-LED mode.

(1) I = Input, O = Output, P = Power, I/O = Digital input/output

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