Datasheet

bq500210
SLUSAL8C –JUNE 2011–REVISED SEPTEMBER 2012 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
OPERATING TEMPERATURE TOP SIDE
ORDERABLE PART NUMBER PIN COUNT SUPPLY PACKAGE
RANGE, T
A
MARKING
bq500210RGZR 48 pin Reel of 2500 QFN bq500210
-40°C to 110°C
bq500210RGZT 48 pin Reel of 250 QFN bq500210
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN MAX
Voltage applied at V33D to DGND –0.3 3.8 V
Voltage applied at V33A to AGND –0.3 3.8 V
Voltage applied to any pin
(2)
–0.3 3.8 V
Storage temperature,T
STG
–40 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to GND.
THERMAL INFORMATION
bq500210
THERMAL METRIC
(1)
RGZ UNITS
48 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
28.4
θ
JC(top)
Junction-to-case(top) thermal resistance
(3)
13.9
θ
JB
Junction-to-board thermal resistance
(4)
5.3
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.2
ψ
JB
Junction-to-board characterization parameter
(6)
5.2
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance
(7)
1.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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